公开(公告)号：US5023674A

公开(公告)日：1991-06-11

申请号：US593502

申请日：1990-10-04

Applicant: Kohki Hikosaka ,  Yasutake Hirachi

Inventor： Kohki Hikosaka ,  Yasutake Hirachi

IPC: H01L29/205 ,  H01L29/36 ,  H01L29/43 ,  H01L29/778

CPC classification number: H01L29/205 ,  H01L29/365 ,  H01L29/432 ,  H01L29/7784

Abstract: A field effect transistor includes a semiconductor substrate, first and second semiconductor layers formed on the semiconductor substrate, and third semiconductor layers located between the first and second semiconductor layers. The third semiconductor layers have a forbidden band width narrower than those in the first and second semiconductor layers and form a quantum well. The third semiconductor layers include a doping layer such as planar-doping or high doping, and a channel is formed in the third semiconductor layers along the quantum well. The electrons supplied from the doped layer are confined by the quantum well and form a quasi-two-dimensional electron gas.

Abstract translation: 场效应晶体管包括半导体衬底，形成在半导体衬底上的第一和第二半导体层以及位于第一和第二半导体层之间的第三半导体层。 第三半导体层的禁带宽度比第一和第二半导体层中窄，形成量子阱。 第三半导体层包括诸如平面掺杂或高掺杂的掺杂层，沿着量子阱在第三半导体层中形成沟道。 从掺杂层提供的电子被量子阱限制并形成准二维电子气。

公开(公告)号：US5698868A

公开(公告)日：1997-12-16

申请号：US384387

申请日：1995-02-03

Applicant: Yuji Awano ,  Yasutake Hirachi ,  Kohki Hikosaka

Inventor： Yuji Awano ,  Yasutake Hirachi ,  Kohki Hikosaka

IPC: H01L29/812 ,  H01L21/331 ,  H01L21/338 ,  H01L29/08 ,  H01L29/205 ,  H01L29/68 ,  H01L29/73 ,  H01L29/737 ,  H01L29/772 ,  H01L29/778 ,  H01L31/0328

CPC classification number: H01L29/0891 ,  H01L29/205 ,  H01L29/7371 ,  H01L29/7722 ,  H01L29/7781 ,  H01L29/7787

Abstract: A high-speed heterojunction transistor includes a first region for controlling current, and a second region for receiving carriers which have passed the first region. An energy level difference between a lowermost valley of energy and an upper valley of energy in the conduction band of a semiconductor material constituting the second region is greater than that of a semiconductor material constituting the first region.

Abstract translation: 高速异质结晶体管包括用于控制电流的第一区域和用于接收已经通过第一区域的载体的第二区域。 构成第二区域的半导体材料的导带中的最低能量谷和能量上部能级之间的能级差大于构成第一区域的半导体材料的能级差。

公开(公告)号：US5144378A

公开(公告)日：1992-09-01

申请号：US774137

申请日：1991-10-15

Applicant: Kohki Hikosaka

Inventor： Kohki Hikosaka

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/205 ,  H01L29/267 ,  H01L29/43 ,  H01L29/778

CPC classification number: H01L29/267 ,  H01L29/205 ,  H01L29/432 ,  H01L29/7783

Abstract: A semiconductor device comprises a substrate, a channel layer provided on the substrate and formed of an undoped first semiconductor material containing indium arsenide, a two-dimensional electron gas formed in the channel layer as a substantially scatter-free path of electrons, an electron supplying layer provided on the channel layer to form a heterojunction interface with the channel layer, a source electrode provided on the electron supplying layer for injecting electrons, a drain electrode provided on the electron supplying layer for collecting electrons and a gate electrode provided on the electron supplying layer for controlling the passage of the electrons in the two-dimensional electron gas. The electron supplying layer comprises a second compound semiconductor material having a lattice constant matching to the channel layer and doped to the n-type to form the two-dimensional electron gas. The second compound semiconductor material has a valence band having an energy level higher than the conduction band of the channel layer at the heterojunction interface, and the second compound semiconductor material is doped to a concentration level such that the Fermi level is located between the valence band and the conduction band of the second compound semiconductor material forming the electron supplying layer.

Abstract translation: 半导体器件包括衬底，设置在衬底上并由包含砷化铟的未掺杂的第一半导体材料形成的沟道层，形成在沟道层中的二维电子气体作为电子的基本无散射的路径，电子供应 层，设置在沟道层上以形成与沟道层的异质结界面，设置在用于注入电子的电子供给层上的源电极，设置在用于收集电子的电子供应层上的漏极和设置在电子供给上的栅电极 用于控制二维电子气中的电子通过的层。 电子供给层包括具有与沟道层匹配的晶格常数并掺杂到n型以形成二维电子气的第二化合物半导体材料。 第二化合物半导体材料具有能量水平高于异质结界面处的沟道层的导带的价带，并且第二化合物半导体材料被掺杂到浓度水平，使得费米能级位于价带之间 以及形成电子供给层的第二化合物半导体材料的导带。

公开(公告)号：US4477311A

公开(公告)日：1984-10-16

申请号：US561967

申请日：1983-12-15

Applicant: Takashi Mimura ,  Kohki Hikosaka ,  Kouichiro Odani

Inventor： Takashi Mimura ,  Kohki Hikosaka ,  Kouichiro Odani

IPC: H01L21/31 ,  C23C14/56 ,  C30B23/02 ,  H01J37/32 ,  H01L21/20 ,  H01L21/203 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/318 ,  H01L21/324 ,  H01L21/306 ,  H01L7/36 ,  B05D5/12 ,  C23C13/08

CPC classification number: C23C14/56 ,  C30B23/02 ,  H01J37/32 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/3185 ,  H01L21/3245 ,  Y10S148/017 ,  Y10S148/022 ,  Y10S148/169 ,  Y10S438/913

Abstract: MOlecular beam epitaxy (MBE) requires that the surface of a substrate on which a semiconductor layer is formed by MBE be clean. Physical etching damages the substrate, while usual chemical etching damages vacuum pumps and contaminates MBE apparatuses. Hydrogen plasma etching can clean a substrate without damaging a substrate and a vacuum pump and without contaminating an MBE apparatus. Further, by combining MBE with formation of a protective layer without breaking the vacuum used in MBE, diffusion of an impurity in the semiconductor layer formed by MBE can be greatly decreased during a subsequent high-temperature heat treatment.

Abstract translation: 分子束外延（MBE）要求通过MBE形成半导体层的衬底的表面是干净的。 物理蚀刻损坏基板，而通常的化学蚀刻损坏真空泵并污染MBE装置。 氢等离子体蚀刻可以清洁基板而不损坏基板和真空泵，而不污染MBE装置。 此外，通过将MBE与形成保护层组合而不破坏MBE中使用的真空，在随后的高温热处理期间，可以大大降低由MBE形成的半导体层中的杂质的扩散。