公开(公告)号：US06115282A

公开(公告)日：2000-09-05

申请号：US215906

申请日：1998-12-18

申请人： Koichi Abe ,  Takashi Inui ,  Kohsuke Ikeda ,  Toshiyuki Ishiuchi

发明人： Koichi Abe ,  Takashi Inui ,  Kohsuke Ikeda ,  Toshiyuki Ishiuchi

IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/00

CPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C8/18

摘要： The objective is to provide a type of dynamic memory which does not adversely affect the data, even when noise is superimposed on the RAS signal.

摘要翻译： 目的是提供一种不会对数据产生不利影响的动态存储器，即使当噪声叠加在RAS信号上时也是如此。

公开(公告)号：US5703499A

公开(公告)日：1997-12-30

申请号：US630312

申请日：1996-04-10

申请人： Koichi Abe ,  Takashi Inui

发明人： Koichi Abe ,  Takashi Inui

IPC分类号： G11C11/409 ,  G11C8/06 ,  G11C11/417 ,  H03K19/0175

CPC分类号： G11C8/06

摘要： An input circuit for a memory address bit operates at high operating speed. A PMOS transistor 112 is provided between a supply line for 1/2V.sub.CC and a node N11. When not in operation, node N11 of input portion 11A is precharged not to the power supply voltage V.sub.CC, but to 1/2V.sub.CC, a potential halfway between the power supply voltage V.sub.CC and 0 V. Another PMOS transistor 117 is provided between a PMOS transistor 111 and node N11 of the input stage to prevent leakage between V.sub.CC and 1/2V.sub.CC. As a result, an enable signal ENB goes to a high level, the circuit enters the operating state, address bit signal Ai is input, and the time needed to shift the level of node N11 to V.sub.CC or 0 V becomes short.

摘要翻译： 用于存储器地址位的输入电路以高操作速度工作。 PMOS晶体管112设在用于+ E的电源线，1/2 + EE VCC和节点N11之间。 当不工作时，输入部分11A的节点N11不对电源电压VCC进行预充电，而是对电源电压VCC和0V之间的电位的+ E，fra 1/2 + EE VCC进行预充电。另一个PMOS晶体管 117设置在输入级的PMOS晶体管111和节点N11之间，以防止VCC和+ E之间的泄漏，1/2 + EE VCC。 结果，使能信号ENB变为高电平，电路进入工作状态，输入地址位信号Ai，将节点N11的电平移位到VCC或0V所需的时间变短。

公开(公告)号：US07770132B2

公开(公告)日：2010-08-03

申请号：US12045839

申请日：2008-03-11

申请人： Takashi Inui ,  Mizuho Tadokoro

发明人： Takashi Inui ,  Mizuho Tadokoro

IPC分类号： G06F3/048

CPC分类号： G09G5/14 ,  G06F9/451

摘要： A display device which displays a plurality of objects on a screen has a group configuration storage section for storing association information indicating the association between each of the plurality of objects and one of a plurality of groups, a group priority level storage section for storing group display priority levels which are priority levels for displaying each of the objects associated with one of the groups at the front of the objects associated with the other groups, an object priority level storage section for storing object display priority levels which are priority levels for displaying one of the objects associated with one of the groups at the front of the others, an object priority level changing section for changing the object display priority level while the association information is maintained, and a display section for displaying the plurality of objects according to the group display priority levels and the object display priority levels.

摘要翻译： 在屏幕上显示多个对象的显示装置具有：组配置存储部，用于存储指示多个对象中的每一个与多个组中的一个的关联的关联信息;组优先级存储部，用于存储组显示 优先级，其是用于显示与与其他组相关联的对象的前面的组中的一个组相关联的每个对象的优先级;对象优先级级别存储部分，用于存储作为用于显示其他组中的一个的优先级的对象显示优先级 与其他前面的组中的一个相关联的对象，用于在保持关联信息的同时改变对象显示优先级的对象优先级改变部分和根据组显示显示多个对象的显示部分 优先级和对象显示优先级。

公开(公告)号：US20050156571A1

公开(公告)日：2005-07-21

申请号：US11020993

申请日：2004-12-22

申请人： Takashi Inui ,  Mizuho Tadokoro

发明人： Takashi Inui ,  Mizuho Tadokoro

IPC分类号： G06F1/28 ,  H02J7/00 ,  H02J7/34

CPC分类号： H02J7/0075

摘要： An information processing apparatus driven by an AC power supply or a rechargeable battery has a charge directing unit which initiates charging of the battery from the AC power supply, provided that the remaining amount of power of the battery is lower than a predetermined charge-start-criteria level and that the information processing apparatus is driven by the AC power supply. Also included is a drive history storage which stores a drive history including information indicating which of the AC power supply and the battery was driving the information processing apparatus in each time period in the past. A recharge-start-criteria-level-setting unit sets the charge-start-criteria level on the basis of the drive history.

摘要翻译： 由AC电源或可再充电电池驱动的信息处理装置具有充电指示单元，该充电指示单元从AC电源开始对电池充电，只要电池的剩余电量低于预定充电开始时间， 信号处理装置由AC电源驱动。 还包括一个驱动历史存储器，其存储包括在过去的每个时间段中包括交流电源和电池正在驱动信息处理装置的信息的驱动历史。 充值启动标准级别设置单元根据驱动历史设置充电开始标准级别。

公开(公告)号：US5574693A

公开(公告)日：1996-11-12

申请号：US473405

申请日：1995-06-07

申请人： Takashi Inui ,  Kiyotaka Okuzawa ,  Yoshihiro Ogata

发明人： Takashi Inui ,  Kiyotaka Okuzawa ,  Yoshihiro Ogata

IPC分类号： B60R9/042 ,  G11C13/00

CPC分类号： G11C8/08 ,  G11C11/401 ,  G11C2029/2602 ,  G11C29/34

摘要： A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

摘要翻译： 一种半导体存储器件，其特征在于可以缩短半导体存储器件的干扰测试时间，并且可以削减功耗。 在本发明的半导体存储器件的干扰测试中，以对应于元件隔离布局的规定间隔同时选择多个字线。 当对应于元件隔离布局选择字线时，可以排除由元件隔离状态引起的干扰。 由于同时选择多个字线，所以可以缩短操作时间。 由于在读出放大器未复位的同时，字线保持在选择状态，所以尽管同时选择了多个字线，功耗也没有增加。

公开(公告)号：US5455796A

公开(公告)日：1995-10-03

申请号：US105203

申请日：1993-08-10

申请人： Takashi Inui ,  Kiyotaka Okuzawa ,  Yoshihiro Ogata

发明人： Takashi Inui ,  Kiyotaka Okuzawa ,  Yoshihiro Ogata

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C29/12 ,  G11C29/34 ,  H01L27/10 ,  G11C11/40

CPC分类号： G11C29/34

摘要： A semiconductor memory device characterized by the fact that the disturb test time of the semiconductor memory/device can be shortened, and the power consumption can be cut.In the disturb test for the semiconductor memory device in this invention, multiple word lines are selected at the same time with a prescribed interval corresponding to the element isolation layout. As the word lines are selected corresponding to the element isolating layout, the interference caused by the element isolation state can be excluded. Since multiple word lines are selected at the same time, the time of operation can be shortened. Since the word lines are maintained in the selected state while the sense amplifiers are not reset, there is no increase in the power consumption although multiple word lines are selected at the same time.

摘要翻译： 一种半导体存储器件，其特征在于可以缩短半导体存储器/器件的干扰测试时间，并且可以削减功耗。 在本发明的半导体存储器件的干扰测试中，以对应于元件隔离布局的规定间隔同时选择多个字线。 当对应于元件隔离布局选择字线时，可以排除由元件隔离状态引起的干扰。 由于同时选择多个字线，所以可以缩短操作时间。 由于在读出放大器未复位的同时，字线保持在选择状态，所以尽管同时选择了多个字线，功耗也没有增加。

公开(公告)号：US5055717A

公开(公告)日：1991-10-08

申请号：US398339

申请日：1989-08-24

申请人： Atsushi Naito ,  Kiyoshi Nakatsuka ,  Seiichi Yamamoto ,  Takashi Inui ,  Tomohiro Suzuki

发明人： Atsushi Naito ,  Kiyoshi Nakatsuka ,  Seiichi Yamamoto ,  Takashi Inui ,  Tomohiro Suzuki

IPC分类号： G09G5/395 ,  G11C7/10

CPC分类号： G11C7/1075 ,  G09G5/395 ,  G11C7/103

摘要： Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data. Upon decoding the serial sequence selection data of the partial address buffer, a plurality of MOS transistors included in the selector portion are rendered conductive in sequence in response to respective control signals applied to the gates thereof to connect the plurality of data registers via their output buffers to respective output drivers in a sequence determined by the decoded selection data of the partial address buffer for serial data output in the selected serial data output sequence.

摘要翻译： 数据选择器电路包括通过相应的输出缓冲器并行连接到多个输出驱动器的多个数据寄存器，其中解码器和选择器部分插在输出缓冲器和输出驱动器之间，用于选择性地提供多个串行数据输出 从数据寄存器到输出驱动器的序列，而不是否则将发生的多个数据寄存器的并行数据输出格式。 解码器和选择器部分由具有串行序列选择数据的部分地址缓冲器控制。 在对部分地址缓冲器的串行序列选择数据进行解码时，响应于施加到其栅极的相应控制信号，包括在选择器部分中的多个MOS晶体管依次被导通，以经由其输出缓冲器连接多个数据寄存器 以由所选择的串行数据输出序列中输出的串行数据的部分地址缓冲器的解码选择数据确定的序列分配给相应的输出驱动器。

公开(公告)号：US07395441B2

公开(公告)日：2008-07-01

申请号：US11284582

申请日：2005-11-22

申请人： Takashi Inui ,  Mizuho Tadokoro ,  Noritoshi Yoshiyama

发明人： Takashi Inui ,  Mizuho Tadokoro ,  Noritoshi Yoshiyama

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F11/00

CPC分类号： G06F1/3203

摘要： A data processing system capable of specifying impeding factors that impede power savings is disclosed. The data processing system includes a central processing unit, an operation mode detection unit, and an impeding factors specifying unit. The central processing unit has multiple operation modes, and each of the operation modes has a different rate of power consumption. The operation mode detection unit detects an operation mode of the central processing unit. Based on a history of operation modes of the central processing unit that was detected by the operation mode detection unit, the impeding factors specifying unit specifies a device that is considered as an impeding factor to power savings for the data processing system.

摘要翻译： 公开了能够指定阻碍功率节省的阻碍因素的数据处理系统。 数据处理系统包括中央处理单元，操作模式检测单元和阻碍因子确定单元。 中央处理单元具有多种操作模式，每种操作模式具有不同的功耗率。 操作模式检测单元检测中央处理单元的操作模式。 根据由操作模式检测单元检测到的中央处理单元的操作模式的历史，阻碍因子指定单元指定被认为是数据处理系统的节能的阻碍因素的设备。

公开(公告)号：US07024507B2

公开(公告)日：2006-04-04

申请号：US10065060

申请日：2002-09-13

申请人： Takashi Inui ,  Masahiko Nomura ,  Noritoshi Yoshiyama

发明人： Takashi Inui ,  Masahiko Nomura ,  Noritoshi Yoshiyama

IPC分类号： G06F13/00

CPC分类号： G06F9/4411 ,  G06F13/4081

摘要： A user specifies, in advance, the expansion devices which he/she does not want to remove among the expansion devices which are attachable/detachable with respect to the PC, and the specified expansion devices are excluded from a list displayed later for the user to select an expansion device to remove. Besides, whether to display expansion devices in the list is specified to an BIOS and the information referenced by the BIOS is stored in an NVRAM.

摘要翻译： 用户预先指定他/她不想在相对于PC可附接/拆卸的扩展设备之间移除的扩展设备，并且将指定的扩展设备从稍后为用户显示的列表中排除 选择要移除的扩展设备。 此外，是否将列表中的扩展设备显示给BIOS，并将BIOS引用的信息存储在NVRAM中。

公开(公告)号：US20050156570A1

公开(公告)日：2005-07-21

申请号：US11015820

申请日：2004-12-17

申请人： Takashi Inui ,  Mizuho Tadokoro

发明人： Takashi Inui ,  Mizuho Tadokoro

IPC分类号： H02J7/04 ,  H01M10/42 ,  H01M10/44 ,  H02J7/00 ,  H02J7/02

CPC分类号： H02J7/0075 ,  H02J7/0047 ,  H02J2007/0049 ,  H02J2007/005

摘要： An information processing apparatus that is driven by a rechargeable battery, wherein the battery is depleted from a fully charged state and repeatedly charged and discharged, comprises a full charge capacity acquisition unit for acquiring a present full charge capacity of the battery which the battery has at the present time, a total charge acquiring unit for acquiring information indicating a total amount of charge provided to the battery in a time period from a start time of using the battery until the present full charge capacity is acquired, and a restoring unit for performing a battery restoration in which the battery is fully discharged or fully charged in order to recover the full charge capacity if it is determined that the present full charge capacity is smaller than an expected full charge capacity that the battery should have depending on the information.

摘要翻译： 一种由可再充电电池驱动的信息处理装置，其中电池耗尽完全充电状态并重复充电和放电，包括完全充电容量获取单元，用于获取电池具有的电池的当前完全充电容量 当前时间，一个总计费用获取单元，用于在从使用电池的开始时间到获取当前的完全充电容量之后的时间段中获取指示提供给电池的总电量的信息;以及恢复单元，用于执行 如果确定当前的完全充电容量小于电池应该具有的预期的完全充电容量，则电池完全放电或完全充电以恢复完全充电容量的电池恢复。