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公开(公告)号：US07149113B2
公开(公告)日：2006-12-12
申请号：US11072309
申请日：2005-03-07
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： G11C16/04
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
摘要翻译： 为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮动电极的非易失性存储元件，通过第一（第二）存储来存储半导体中存储单元阵列的缺陷的地址 多晶硅层或非易失性存储元件被编程用于测试半导体集成电路。 结果，在形成非易失性存储元件中不需要特殊的处理。 换句话说，非易失性存储元件可以在形成CMOS器件的过程中形成，并且不需要用于编程的激光束的装置，因为在测试中执行编程。 因此，可以缩短编程所需的时间，因此可以降低测试成本。
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公开(公告)号：US06894944B2
公开(公告)日：2005-05-17
申请号：US10602684
申请日：2003-06-25
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： H01L21/8247 , G11C16/04 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/42 , H01L21/66 , H01L23/532 , H01L23/544 , H01L27/02 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , G11C8/00
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
摘要翻译： 为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮动电极的非易失性存储元件，通过第一（第二）存储来存储半导体中存储单元阵列的缺陷的地址 多晶硅层或非易失性存储元件被编程用于测试半导体集成电路。 结果，在形成非易失性存储元件中不需要特殊的处理。 换句话说，非易失性存储元件可以在形成CMOS器件的过程中形成，并且不需要用于编程的激光束的装置，因为在测试中执行编程。 因此，可以缩短编程所需的时间，因此可以降低测试成本。
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公开(公告)号：US20050152186A1
公开(公告)日：2005-07-14
申请号：US11072309
申请日：2005-03-07
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： H01L21/8247 , G11C16/04 , G11C29/00 , G11C29/04 , G11C29/12 , G11C29/42 , H01L21/66 , H01L23/532 , H01L23/544 , H01L27/02 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
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公开(公告)号：US06611458B2
公开(公告)日：2003-08-26
申请号：US09780393
申请日：2001-02-12
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： G11C1606
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, address for salvaging defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit, thereby, a special process is not needed in forming the nonvolatile memory element, that is, the nonvolatile memory element can be formed in a process of forming CMOS device and apparatus of laser beam for programming is not needed since the programming is carried out in testing, time necessary for programming can be shortened and therefore, testing cost can be reduced.
摘要翻译： 为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮置电极的非易失性存储元件，通过第一层 多晶硅或非易失性存储元件在对半导体集成电路进行测试时被编程，从而在形成非易失性存储元件时不需要特殊工艺，也就是说，可以在形成CMOS器件和器件的过程中形成非易失性存储元件 用于编程的激光束不需要，因为在测试中进行编程，可以缩短编程所需的时间，因此可以降低测试成本。
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公开(公告)号：US20110012206A1
公开(公告)日：2011-01-20
申请号：US12891208
申请日：2010-09-27
IPC分类号： H01L27/088
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。
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公开(公告)号：US07428164B2
公开(公告)日：2008-09-23
申请号：US11717629
申请日：2007-03-14
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
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公开(公告)号：US07200030B2
公开(公告)日：2007-04-03
申请号：US10733270
申请日：2003-12-12
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。
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公开(公告)号：US20080316800A1
公开(公告)日：2008-12-25
申请号：US12222753
申请日：2008-08-15
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。
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公开(公告)号：US20060031655A1
公开(公告)日：2006-02-09
申请号：US11242854
申请日：2005-10-05
申请人： Kei Kato , Masanao Yamaoka , Keiichi Higeta , Kazumasa Yanagisawa , Shigeru Shimada , Kodo Yamauchi , Yoshihiro Shinozaki , Yasuo Taguchi
发明人： Kei Kato , Masanao Yamaoka , Keiichi Higeta , Kazumasa Yanagisawa , Shigeru Shimada , Kodo Yamauchi , Yoshihiro Shinozaki , Yasuo Taguchi
IPC分类号： G06F12/00
CPC分类号： G11C7/106 , G06F17/5045 , G11C7/10 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C2207/104
摘要： The present invention is directed to facilitate change in the specifications of an interface of a memory IP and to improve reusability of the memory IP. A memory module to be mounted on a system LSI or the like is constructed by a basic array and an interface. The basic array is constructed by direct peripheral circuits and a storage circuit. Library data of the basic array is stored in a storage medium such as a CD-R or a magnetic tape and distributed to the user. The library data includes layout pattern data, a logic simulation model defining the operation of the basic array, LSI pattern information such as a layout, device information such as characteristics of a MOS device and layout rules, interface information such as various signal timings, and device specification data such as terminal information.
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公开(公告)号：US08264870B2
公开(公告)日：2012-09-11
申请号：US12891208
申请日：2010-09-27
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。
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