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    Cache memory employing dynamically controlled data array start timing and a microprocessor using the same
    5.
    发明授权
    Cache memory employing dynamically controlled data array start timing and a microprocessor using the same 失效
    使用动态控制的数据阵列启动定时的高速缓存存储器和使用其的微处理器

    公开(公告)号：US06389523B1

    公开(公告)日：2002-05-14

    申请号：US09557220

    申请日：2000-04-25

    申请人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    发明人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    IPC分类号： G06F1206

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

    摘要： A comparator is constituted such that a hit signal &phgr;hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

    摘要翻译： 构成一个比较器，使命中信号phihit是高的，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个错误时，命中信号变低。 当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。 当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。 这种新颖的结构实现了高速缓存操作。 当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

    Cache memory employing dynamically controlled data array start timing and a microcomputer using the same
    6.
    发明授权
    Cache memory employing dynamically controlled data array start timing and a microcomputer using the same 失效
    使用动态控制的数据阵列启动定时的高速缓冲存储器和使用其的微型计算机

    公开(公告)号：US5860127A

    公开(公告)日：1999-01-12

    申请号：US653278

    申请日：1996-05-24

    申请人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    发明人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F12/08

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02B60/1225

    摘要： A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

    摘要翻译： 构成比较器，使得命中信号phi命中为高，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个虚构时，命中信号变低。 当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。 当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。 这种新颖的结构实现了高速缓存操作。 当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

    Cacche memory employing dynamically controlled data array start timing and a microcomputer using the same
    8.
    发明授权
    Cacche memory employing dynamically controlled data array start timing and a microcomputer using the same 失效
    采用动态控制的数据阵列启动定时的Cacche存储器和使用它的微型计算机

    公开(公告)号：US6070234A

    公开(公告)日：2000-05-30

    申请号：US118892

    申请日：1998-07-20

    申请人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    发明人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F12/08

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02B60/1225

    摘要： A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

    摘要翻译： 构成比较器，使得命中信号phi命中为高，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个虚构时，命中信号变低。 当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。 当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。 这种新颖的结构实现了高速缓存操作。 当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

    Data processing system and data processor
    9.
    发明授权
    Data processing system and data processor 有权
    数据处理系统和数据处理器

    公开(公告)号：US07975077B2

    公开(公告)日：2011-07-05

    申请号：US12470988

    申请日：2009-05-22

    申请人： Junichi Nishimoto ,  Takuichiro Nakazawa ,  Koji Yamada ,  Toshihiro Hattori

    发明人： Junichi Nishimoto ,  Takuichiro Nakazawa ,  Koji Yamada ,  Toshihiro Hattori

    IPC分类号： G06F13/38

    CPC分类号： G06F1/32 ,  G06F1/325 ,  G06F1/3265 ,  G06F9/4403 ,  G06F9/4416 ,  G06F13/24 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4045 ,  G06F13/4068 ,  Y02D10/14 ,  Y02D10/151

    摘要： One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.

    摘要翻译： 一个数据处理器设置有用于实现与其他数据处理器的连接的接口。 该接口具有将作为总线主机的其他数据处理器连接到一个数据处理器的内部总线的功能，并且相关的其他数据处理器能够直接从存储器映射到内部总线的外围功能 外部通过接口。 因此，数据处理器可以利用其他数据处理器的外围功能，而不中断执行的程序。 简而言之，一个数据处理器可以共同使用其他数据处理器的外围资源。