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    Semiconductor device semiconductor device testing method, and data processing system
    1.
    发明授权
    Semiconductor device semiconductor device testing method, and data processing system 有权
    半导体器件半导体器件测试方法和数据处理系统

    公开(公告)号：US08803545B2

    公开(公告)日：2014-08-12

    申请号：US12929330

    申请日：2011-01-14

    申请人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

    发明人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

    IPC分类号： G01R31/26

    CPC分类号： G06F1/12 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

    摘要： To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.

    摘要翻译： 为了提供一种包括接口芯片和芯片的半导体器件，以及测量目标信号线和参考信号线，每个包括设置在芯片芯片中的穿硅通孔，并且电连接接口芯片和芯片芯片。 接口芯片将由第一信号发生电路产生的测试时钟输出到核心芯片。 核心芯片包括从测试时钟产生预定测量信号的第二信号产生电路，并以预定的测量信号同时输出到测量目标信号线和参考信号线。 此外，接口芯片通过运算放大器检测经由测量对象信号线和参考信号线输入的多个预定测量信号的相位差，并将测试结果输出到确定电路。

    Semiconductor apparatus
    2.
    发明授权
    Semiconductor apparatus 失效
    半导体装置

    公开(公告)号：US08604835B2

    公开(公告)日：2013-12-10

    申请号：US12871564

    申请日：2010-08-30

    申请人： Koji Kuroki ,  Ryuji Takishita

    发明人： Koji Kuroki ,  Ryuji Takishita

    IPC分类号： G01R25/00 ,  H03D13/00

    CPC分类号： H03L7/085 ,  G11C7/222 ,  H03K5/249 ,  H03L7/0814 ,  H03L7/0816

    摘要： In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).

    摘要翻译： 在半导体器件中，在GND和两个感测节点之间提供第一至第三对nMOS晶体管，并且在两个感测节点和电源之间提供第一至第三对pMOS晶体管对。 第一内部时钟信号及其反相信号分别被提供给第一对nMOS晶体管和第二对nMOS晶体管的栅极。 互补的外部时钟信号被提供给第三对nMOS晶体管和第三对pMOS晶体管的栅极。 第二内部时钟信号的反相形式和第二内部时钟信号被提供给第一和第二对pMOS晶体管的栅极。 两个感测节点连接到差分放大器的输入。 差分放大器的输出由锁存电路锁存。 还提供了均衡电路对两个感测节点进行预充电/均衡（图2）。

    DUTY DETECTION CIRCUIT, DLL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING SAME
    5.
    发明申请
    DUTY DETECTION CIRCUIT, DLL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING SAME 审中-公开
    占空比检测电路，DLL电路和具有相同功能的半导体器件

    公开(公告)号：US20070152680A1

    公开(公告)日：2007-07-05

    申请号：US11553908

    申请日：2006-10-27

    申请人： Hiroki FUJISAWA ,  Ryuji TAKISHITA

    发明人： Hiroki FUJISAWA ,  Ryuji TAKISHITA

    IPC分类号： G01R27/28

    CPC分类号： H03L7/0814 ,  H03K5/1565 ,  H03L7/07 ,  H03L7/085

    摘要： Accurate duty detection is enabled by performing duty detection once every two cycles while delaying detection of one clock logic level by a half cycle, and presetting the potential of a common contact to an initial set value during the delay time. A DLL circuit employing a divide-by-two scheme is provided with separate duty detection circuits for even-numbered and odd-numbered cycles to detect duties of the respective cycles, respectively. The DLL circuit having this configuration and a semiconductor device having such DLL circuit are capable of accurate timing adjustment to the clock.

    摘要翻译： 通过每两个周期一次执行占空比检测就可以实现准确的占空比检测，同时延迟一个时钟逻辑电平检测一个半个周期，并在延迟时间内将公共端子的电位预设为初始设定值。 采用二分之一方案的DLL电路分别提供用于偶数和奇数周期的单独的占空比检测电路，以分别检测各个周期的占空比。 具有这种结构的DLL电路和具有这种DLL电路的半导体器件能够精确地对时钟进行定时调整。

    Semiconductor device semiconductor device testing method, and data processing system
    8.
    发明申请
    Semiconductor device semiconductor device testing method, and data processing system 有权
    半导体器件半导体器件测试方法和数据处理系统

    公开(公告)号：US20110175639A1

    公开(公告)日：2011-07-21

    申请号：US12929330

    申请日：2011-01-14

    申请人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

    发明人： Hideyuki Yoko ,  Kentaro Hara ,  Ryuji Takishita

    IPC分类号： G01R31/26 ,  H01L23/48

    CPC分类号： G06F1/12 ,  G11C5/04 ,  G11C29/02 ,  G11C29/025 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

    摘要： To provide a semiconductor device including an interface chip and a core chip and a measurement-target signal line and a reference signal line each including a through silicon via provided in the core chip and electrically connecting the interface chip and the core chip. The interface chip outputs a test clock generated by a first signal generation circuit to the core chip. The core chip includes a second signal generation circuit that generates a predetermined measurement signal from the test clock, and outputs the predetermined measurement signal to the measurement-target signal line and the reference signal line in a simultaneous manner. Further, the interface chip detects a phase difference of a plurality of predetermined measurement signals input via the measurement-target signal line and the reference signal line by an operational amplifier, and outputs a test result to a determination circuit.

    摘要翻译： 为了提供一种包括接口芯片和芯片的半导体器件，以及测量目标信号线和参考信号线，每个包括设置在芯片芯片中的穿硅通孔，并且电连接接口芯片和芯片芯片。 接口芯片将由第一信号发生电路产生的测试时钟输出到核心芯片。 核心芯片包括从测试时钟产生预定测量信号的第二信号产生电路，并以预定的测量信号同时输出到测量目标信号线和参考信号线。 此外，接口芯片通过运算放大器检测经由测量对象信号线和参考信号线输入的多个预定测量信号的相位差，并将测试结果输出到确定电路。

    SEMICONDUCTOR APPARATUS
    9.
    发明申请
    SEMICONDUCTOR APPARATUS 失效

    公开(公告)号：US20110050304A1

    公开(公告)日：2011-03-03

    申请号：US12871564

    申请日：2010-08-30

    申请人： Koji Kuroki ,  Ryuji Takishita

    发明人： Koji Kuroki ,  Ryuji Takishita

    IPC分类号： H03L7/06

    CPC分类号： H03L7/085 ,  G11C7/222 ,  H03K5/249 ,  H03L7/0814 ,  H03L7/0816

    摘要： In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).

    摘要翻译： 在半导体器件中，在GND和两个感测节点之间提供第一至第三对nMOS晶体管，并且在两个感测节点和电源之间提供第一至第三对pMOS晶体管对。 第一内部时钟信号及其反相信号分别被提供给第一对nMOS晶体管和第二对nMOS晶体管的栅极。 互补的外部时钟信号被提供给第三对nMOS晶体管和第三对pMOS晶体管的栅极。 第二内部时钟信号的反相形式和第二内部时钟信号被提供给第一和第二对pMOS晶体管的栅极。 两个感测节点连接到差分放大器的输入。 差分放大器的输出由锁存电路锁存。 还提供了均衡电路对两个感测节点进行预充电/均衡（图2）。

    DLL circuit and semiconductor device including the same
    10.
    发明授权
    DLL circuit and semiconductor device including the same 失效
    DLL电路和包括其的半导体器件

    公开(公告)号：US07576579B2

    公开(公告)日：2009-08-18

    申请号：US11892525

    申请日：2007-08-23

    申请人： Hiroki Fujisawa ,  Ryuji Takishita

    发明人： Hiroki Fujisawa ,  Ryuji Takishita

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812

    摘要： A DLL circuit includes a first delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK1, a second delay adjusting circuit that adjusts an amount of delay of a frequency-divided signal CK2, a synthesizing circuit that synthesizes outputs of these delay adjusting circuits to generate an internal clock signal, and supplies the internal clock signal to a real path, a clock driver that receives the output of the first delay adjusting circuit and supplies the output to a replica path, and a clock driver that receives the output of the second delay adjusting circuit. These clock drivers have substantially the same circuit configuration. Accordingly, even when the power supply voltage fluctuates, influences of the fluctuations on the respective frequency-divided signals are almost equal. Thus, deterioration of the function of the DLL circuit due to fluctuations of the power supply voltage can be prevented.

    摘要翻译： DLL电路包括调整分频信号CK1的延迟量的第一延迟调整电路，调整分频信号CK2的延迟量的第二延迟调整电路，合成这些信号的输出的合成电路 延迟调整电路以产生内部时钟信号，并将内部时钟信号提供给实际路径;时钟驱动器，接收第一延迟调整电路的输出并将输出提供给副本路径;以及时钟驱动器，其接收 输出第二延迟调整电路。 这些时钟驱动器具有基本上相同的电路配置。 因此，即使电源电压波动，各分频信号的波动的影响也几乎相等。 因此，可以防止由于电源电压的波动引起的DLL电路的功能的劣化。