公开(公告)号：US07804127B2

公开(公告)日：2010-09-28

申请号：US12155983

申请日：2008-06-12

申请人： Koji Takaya ,  Akiyuki Minami

发明人： Koji Takaya ,  Akiyuki Minami

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7923

摘要： A semiconductor non-volatile memory cell includes an Si (silicon) layer containing substrate including an activation region having a ridge portion; an element separation region embedded in both sides of the activation region; a gate electrode with a gate insulation film inbetween formed over the ridge portion for covering a part of both side surfaces of the ridge portion and an upper surface of the element separation region; a channel forming region formed in a surface layer region of the ridge portion; an extension region formed on both sides of the channel forming region in the longitudinal direction; and an electric charge accumulation layer capable of accumulating electric charges and a sidewall formed on the extension region and one or both of side surfaces of the gate electrode facing with each other in the longitudinal direction.

摘要翻译： 半导体非易失性存储单元包括具有包含具有脊部分的激活区域的含Si（硅）层的衬底; 嵌入激活区域的两侧的元件分离区域; 在所述脊部上形成有栅极绝缘膜的栅电极，用于覆盖所述脊部的两个侧面的一部分和所述元件分离区域的上表面; 形成在所述脊部的表层区域中的沟道形成区域; 在纵向方向上形成在通道形成区域的两侧的延伸区域; 以及能够积聚电荷的电荷积累层和形成在所述延伸区域上的侧壁以及在所述栅极电极的侧表面中的一个或两个在所述纵向方向上彼此面对的电荷累积层。

公开(公告)号：US20090045454A1

公开(公告)日：2009-02-19

申请号：US12155983

申请日：2008-06-12

申请人： Koji Takaya ,  Akiyuki Minami

发明人： Koji Takaya ,  Akiyuki Minami

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7923

摘要： A semiconductor non-volatile memory cell includes an Si (silicon) layer containing substrate including an activation region having a ridge portion; an element separation region embedded in both sides of the activation region; a gate electrode with a gate insulation film inbetween formed over the ridge portion for covering a part of both side surfaces of the ridge portion and an upper surface of the element separation region; a channel forming region formed in a surface layer region of the ridge portion; an extension region formed on both sides of the channel forming region in the longitudinal direction; and an electric charge accumulation layer capable of accumulating electric charges and a sidewall formed on the extension region and one or both of side surfaces of the gate electrode facing with each other in the longitudinal direction.

摘要翻译： 半导体非易失性存储单元包括具有包含具有脊部分的激活区域的含Si（硅）层的衬底; 嵌入激活区域的两侧的元件分离区域; 在所述脊部上形成有栅极绝缘膜的栅电极，用于覆盖所述脊部的两个侧面的一部分和所述元件分离区域的上表面; 形成在所述脊部的表层区域中的沟道形成区域; 在纵向方向上形成在通道形成区域的两侧的延伸区域; 以及能够积聚电荷的电荷积累层和形成在所述延伸区域上的侧壁以及在所述栅极电极的侧表面中的一个或两个在所述纵向方向上彼此面对的电荷累积层。

公开(公告)号：US07601594B2

公开(公告)日：2009-10-13

申请号：US12073881

申请日：2008-03-11

申请人： Koji Takaya

发明人： Koji Takaya

IPC分类号： H01L21/8247

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/792

摘要： A method for fabricating a semiconductor memory, the method including: forming an element isolation region in a concave portion of the semiconductor substrate; forming a layer of a gate electrode material so as to cover the concave portion and the element isolation region; forming a gate electrode by forming a mask on a surface of the layer of a gate electrode material so that a height from an upper surface of the convex portion to the surface of the mask is higher than a height from the surface of the element isolation region to the upper surface of the convex portion and by patterning the layer of the gate electrode material; forming a charge storing layer at least one of side surfaces of the gate electrode in contact with the convex portion; and forming a sidewall on a part of the charge storing layer.

摘要翻译： 一种制造半导体存储器的方法，所述方法包括：在半导体衬底的凹部中形成元件隔离区; 形成栅电极层，以覆盖凹部和元件隔离区; 通过在栅极材料层的表面上形成掩模来形成栅极电极，使得从凸部的上表面到掩模的表面的高度高于从元件隔离区域的表面的高度 到凸起部分的上表面并且通过图案化栅电极材料的层; 形成与所述凸部接触的所述栅电极的至少一个侧面的电荷存储层; 以及在所述电荷存储层的一部分上形成侧壁。

公开(公告)号：US07371635B2

公开(公告)日：2008-05-13

申请号：US10897029

申请日：2004-07-23

申请人： Koji Takaya

发明人： Koji Takaya

IPC分类号： H01L21/8242

CPC分类号： H01L27/11502 ,  H01L21/84 ,  H01L27/11507 ,  H01L27/1203

摘要： A method of manufacturing a semiconductor device includes: forming a transistor with first and second ends of a main current path, and a control electrode, covering the transistor with a first insulating film, forming first through third openings that expose the first and second ends and the control electrode, and burying or filling first to third conductive materials in the first to third openings respectively, forming the ferroelectric capacitor by laminating the first electrode, the ferroelectric film, and the second electrode, laminating the second insulating film and the moisture diffusion protective film, forming the fourth opening to expose the third conductive material through the second insulating film and the moisture diffusion protective film, and forming a first wiring layer, which has electrical connection with the control electrode.

摘要翻译： 一种制造半导体器件的方法包括：形成具有主电流路径的第一和第二端的晶体管和控制电极，用第一绝缘膜覆盖晶体管，形成第一至第三开口，其暴露第一和第二端;以及 控制电极，分别在第一至第三开口中埋入或填充第一至第三导电材料，通过层叠第一电极，铁电体膜和第二电极形成铁电电容器，层叠第二绝缘膜和水分扩散保护层 膜，形成第四开口以通过第二绝缘膜和水分扩散保护膜暴露第三导电材料，并形成与控制电极电连接的第一布线层。

公开(公告)号：US20080254585A1

公开(公告)日：2008-10-16

申请号：US12073881

申请日：2008-03-11

申请人： Koji Takaya

发明人： Koji Takaya

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/792

摘要： A method for fabricating a semiconductor memory, the method including: forming an element isolation region in a concave portion of the semiconductor substrate; forming a layer of a gate electrode material so as to cover the concave portion and the element isolation region; forming a gate electrode by forming a mask on a surface of the layer of a gate electrode material so that a height from an upper surface of the convex portion to the surface of the mask is higher than a height from the surface of the element isolation region to the upper surface of the convex portion and by patterning the layer of the gate electrode material; forming a charge storing layer at least one of side surfaces of the gate electrode in contact with the convex portion; and forming a sidewall on a part of the charge storing layer.

摘要翻译： 一种制造半导体存储器的方法，所述方法包括：在半导体衬底的凹部中形成元件隔离区; 形成栅电极层，以覆盖凹部和元件隔离区; 通过在栅极材料层的表面上形成掩模来形成栅极电极，使得从凸部的上表面到掩模的表面的高度高于从元件隔离区域的表面的高度 到凸起部分的上表面并且通过图案化栅电极材料的层; 形成与所述凸部接触的所述栅电极的至少一个侧面的电荷存储层; 以及在所述电荷存储层的一部分上形成侧壁。

公开(公告)号：US20070010066A1

公开(公告)日：2007-01-11

申请号：US11425708

申请日：2006-06-22

申请人： Koji Takaya

发明人： Koji Takaya

IPC分类号： H01L21/20

CPC分类号： H01L21/76852 ,  H01L21/02071 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65

摘要： A method for manufacturing a semiconductor device is disclosed, which comprises the steps of (i) forming a circuit element on a semiconductor substrate, (ii) forming a dielectric that covers the circuit element, (iii) forming a first electrode on the dielectric, (iv) forming a ferroelectric film on the first electrode, (v) forming a second electrode on the ferroelectric film, (vi) forming a hardmask on the second electrode, (vii) etching the first electrode, the ferroelectric film, and the second electrode using the hardmask as an etching mask, and (viii) removing the hardmask and redeposition that is attached after said etching to a sidewall of the ferroelectric film simultaneously.

摘要翻译： 公开了一种制造半导体器件的方法，其包括以下步骤：（i）在半导体衬底上形成电路元件，（ii）形成覆盖电路元件的电介质，（iii）在电介质上形成第一电极， （iv）在第一电极上形成铁电体膜，（v）在铁电体膜上形成第二电极，（vi）在第二电极上形成硬掩模，（vii）蚀刻第一电极，铁电体膜和第二电极 使用硬掩模作为蚀刻掩模的电极，以及（viii）将所述蚀刻后附着的硬掩模和再沉积同时移除到铁电体膜的侧壁。

公开(公告)号：US20050145985A1

公开(公告)日：2005-07-07

申请号：US10897012

申请日：2004-07-23

申请人： Koji Takaya

发明人： Koji Takaya

IPC分类号： H01L23/52 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/57 ,  H01L28/65

摘要： The present invention provides a method of manufacturing a semiconductor device that can inhibit deterioration of the ferroelectric film cased by hydrogen generated in a wiring layer. The method of manufacturing a semiconductor device includes steps of forming the ferroelectric capacitor by laminating first electrode 8, ferroelectric film 9, second electrode 10, covering the ferroelectric capacitor by insulating film 11, forming opening 13d that exposes the second electrode 10 on the insulating film 11, depositing or forming conductive hydrogen protective film 20, forming wiring layer 14 on the conductive hydrogen protective film 20, and patterning the wiring layer 14 and the conductive hydrogen protective layer 20 after forming the wiring layer 14.

摘要翻译： 本发明提供一种制造半导体器件的方法，该半导体器件能够抑制由布线层中产生的氢所引起的铁电体膜的劣化。 制造半导体器件的方法包括以下步骤：通过层叠第一电极8，铁电体膜9，第二电极10，通过绝缘膜11覆盖铁电电容器形成铁电电容器，形成开口13d，使第二电极10暴露在绝缘层上 膜11，沉积或形成导电氢保护膜20，在导电氢保护膜20上形成布线层14，以及在形成布线层14之后图案化布线层14和导电氢保护层20。

公开(公告)号：US20080197404A1

公开(公告)日：2008-08-21

申请号：US12003313

申请日：2007-12-21

申请人： Koji Takaya

发明人： Koji Takaya

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L29/40117 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7923

摘要： A semiconductor memory device is fabricated by: forming a device isolation region in a recessed portion of a semiconductor substrate having an irregularly-shaped portion; forming a gate electrode wiring trench in a direction orthogonal to a longitudinal direction of an active region which is a projecting portion of the semiconductor substrate having the irregularly-shaped portion in the device isolation region; forming a gate electrode material layer so as to fill the gate electrode wiring trench; forming a gate electrode by patterning the layer formed of the gate electrode material; forming an active region by etching the device isolation region; forming a charge storage layer on at least one side surface of the gate electrode, the surface being adjacent to the projecting portion of the semiconductor substrate having the irregularly-shaped portion; and forming a side wall on at least a part of the charge storage layer.

摘要翻译： 半导体存储器件通过以下方式制造：在具有不规则形状的部分的半导体衬底的凹陷部分中形成器件隔离区; 在与所述器件隔离区域中具有不规则形状部分的所述半导体衬底的突出部分的有源区的纵向正交的方向上形成栅电极布线沟槽; 形成栅电极材料层以填充栅电极布线沟槽; 通过图案化由栅电极材料形成的层来形成栅电极; 通过蚀刻器件隔离区域形成有源区; 在所述栅电极的至少一个侧表面上形成电荷存储层，所述表面与所述半导体衬底的具有所述不规则形状部分的所述突出部分相邻; 以及在所述电荷存储层的至少一部分上形成侧壁。

公开(公告)号：US07273760B2

公开(公告)日：2007-09-25

申请号：US10897012

申请日：2004-07-23

申请人： Koji Takaya

发明人： Koji Takaya

IPC分类号： H01L21/00

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/57 ,  H01L28/65

摘要： The present invention provides a method of manufacturing a semiconductor device that can inhibit deterioration of the ferroelectric film cased by hydrogen generated in a wiring layer. The method of manufacturing a semiconductor device includes steps of forming the ferroelectric capacitor by laminating first electrode 8, ferroelectric film 9, second electrode 10, covering the ferroelectric capacitor by insulating film 11, forming opening 13d that exposes the second electrode 10 on the insulating film 11, depositing or forming conductive hydrogen protective film 20, forming wiring layer 14 on the conductive hydrogen protective film 20, and patterning the wiring layer 14 and the conductive hydrogen protective layer 20 after forming the wiring layer 14.

摘要翻译： 本发明提供一种制造半导体器件的方法，该半导体器件能够抑制由布线层中产生的氢所引起的铁电体膜的劣化。 制造半导体器件的方法包括以下步骤：通过层叠第一电极8，铁电体膜9，第二电极10，通过绝缘膜11覆盖铁电电容器形成铁电电容器，形成开口13d，使第二电极10暴露在绝缘层上 膜11，沉积或形成导电氢保护膜20，在导电氢保护膜20上形成布线层14，以及在形成布线层14之后图案化布线层14和导电氢保护层20。

公开(公告)号：US20050139881A1

公开(公告)日：2005-06-30

申请号：US10897029

申请日：2004-07-23

申请人： Koji Takaya

发明人： Koji Takaya

IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/76 ,  H01L21/00

CPC分类号： H01L27/11502 ,  H01L21/84 ,  H01L27/11507 ,  H01L27/1203

摘要： A method of manufacturing a semiconductor device includes: forming a transistor with first and second ends 3a and 3b of a main current path, and a control electrode 5, covering the transistor with a first insulating film 6, forming first through third openings that expose the first and second ends 3a and 3b and the control electrode 5, and burying or filling first to third conductive materials 7a-7c in the first to third openings respectively, forming the ferroelectric capacitor by laminating the first electrode 8, the ferroelectric film 9, and the second electrode 10, laminating the second insulating film 11 and the moisture diffusion protective film 12, forming the fourth opening 13c to expose the third conductive material 7c through the second insulating film 11 and the moisture diffusion protective film 12, and forming a first wiring layer 14c, which has electrical connection with the control electrode 5.

摘要翻译： 一种制造半导体器件的方法包括：形成具有主电流通道的第一和第二端3a和3b的晶体管，以及用第一绝缘膜6覆盖晶体管的控制电极5，形成第一至第三开口， 暴露第一和第二端3a和3b以及控制电极5，并分别在第一至第三开口中埋入或填充第一至第三导电材料7a-7c，通过层压第一电极8形成铁电电容器， 强电介质膜9和第二电极10，层叠第二绝缘膜11和水分扩散保护膜12，形成第四开口13c，以通过第二绝缘膜11暴露出第三导电材料7c和水分扩散保护 并且形成与控制电极5电连接的第一布线层14c。