公开(公告)号：US07030728B2

公开(公告)日：2006-04-18

申请号：US10831848

申请日：2004-04-26

申请人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

发明人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

IPC分类号： H01C1/012

CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C17/0656 ,  H01C17/075 ,  H01L27/0802 ,  Y10T29/49082 ,  Y10T29/49087 ,  Y10T29/49098

摘要： A resistor layout and method of forming the resistor are described which achieves improved resistor characteristics, such as resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first resistor element, a second resistor element, a third resistor element, a fourth resistor element, and a fifth resistor element. A layer of protective dielectric is then formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide, such as titanium silicide or cobalt silicide, using a silicidation process. The higher conductivity silicide forms low resistance contacts between the second and fourth resistor elements and between the third and fifth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element, which is the main resistor element. This provides low voltage coefficient of resistance thermal process stability for the resistor.

摘要翻译： 描述了形成电阻器的电阻器布局和方法，其实现了电阻器稳定性和电阻电压系数的改善的电阻器特性。 电阻器由诸如掺杂硅或多晶硅的导电材料形成。 电阻器具有矩形的第一电阻元件，第二电阻元件，第三电阻元件，第四电阻元件和第五电阻元件。 然后在第一，第二和第三电阻器元件上形成保护电介质层，留下第四和第五电阻元件。 然后，使用硅化工艺将暴露的第四和第五电阻器元件中的导电材料改变为硅化物，例如硅化钛或硅化钴。 较高电导率的硅化物在第二和第四电阻元件之间以及第三和第五电阻器元件之间形成低电阻触点。 第二和第三电阻器元件比第一电阻器元件宽，并且向作为主电阻器元件的第一电阻器元件提供低电阻触点。 这为电阻器提供了低电阻系数的电阻热处理稳定性。

公开(公告)号：US06732422B1

公开(公告)日：2004-05-11

申请号：US10037811

申请日：2002-01-04

申请人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

发明人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

IPC分类号： H01C1700

CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C17/0656 ,  H01C17/075 ,  H01L27/0802 ,  Y10T29/49082 ,  Y10T29/49087 ,  Y10T29/49098

摘要： A method of forming a resistor is described which achieves improved resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first, second, third, fourth, and fifth resistor elements. A layer of protective dielectric is formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide to form low resistance contacts between the second and fourth resistor elements and between the second and fourth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element. This provides a low voltage coefficient of resistance and thermal process stability for the resistor.

摘要翻译： 描述形成电阻器的方法，其实现了电阻器稳定性和电阻的电压系数的改善。 电阻器由诸如掺杂硅或多晶硅的导电材料形成。 电阻器具有矩形的第一，第二，第三，第四和第五电阻元件。 在第一，第二和第三电阻器元件上形成保护电介质层，留下第四和第五电阻元件。 然后将暴露的第四和第五电阻器元件中的导电材料改变为硅化物以在第二和第四电阻器元件之间以及第二和第四电阻器元件之间形成低电阻触点。 第二和第三电阻器元件比第一电阻器元件宽，并且向第一电阻器元件提供低电阻触点。 这为电阻器提供了低电阻系数和热处理稳定性。

公开(公告)号：US06436787B1

公开(公告)日：2002-08-20

申请号：US09912735

申请日：2001-07-26

申请人： Wong-Cheng Shih ,  Tzyh-Cheang Lee ,  Wenchi Ting ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

发明人： Wong-Cheng Shih ,  Tzyh-Cheang Lee ,  Wenchi Ting ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

IPC分类号： H01L2120

CPC分类号： H01L28/55 ,  H01L21/3212 ,  H01L28/75 ,  H01L28/91

摘要： A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process is described. A contact node is provided overlying a semiconductor substrate. An intermetal dielectric layer is deposited overlying the contact node. A damascene opening is formed through the intermetal dielectric layer to the contact node. A first metal layer is formed on the bottom and sidewalls of the damascene opening and overlying the intermetal dielectric layer. A first barrier metal layer is is deposited overlying the first metal layer. A dielectric layer is dpeosited overlying the first barrier metal layer. A second barrier metal layer is deposited overlying the dielectric layer. A second metal layer is formed overlying the second barrier metal layer and completely filling the damascene opening. The layers are polished back to leave the first metal layer, the dielectric layer, the first and second barrier metal layers, and the second metal layer only within the damascene opening wherein the first metal layer forms a bottom electrode, the dielectric layer forms a capacitor dielectric, and the second metal layer forms a top electrode to complete fabrication of a crown-type capacitor in the fabrication of an integrated circuit device.

摘要翻译： 描述了使用集成铜镶嵌工艺制造增加的电容金属 - 绝缘体 - 金属电容器的方法。 提供覆盖半导体衬底的接触节点。 沉积在接触节点上的金属间介电层。 通过金属间介质层向接触节点形成镶嵌开口。 第一金属层形成在镶嵌开口的底部和侧壁上并覆盖金属间介电层。 第一阻挡金属层被沉积​​在第一金属层上。 介电层被覆在第一阻挡金属层上方。 沉积在电介质层上的第二阻挡金属层。 形成第二金属层，覆盖第二阻挡金属层并完全填充镶嵌开口。 这些层被抛光回去，以留下第一金属层，电介质层，第一和第二阻挡金属层和第二金属层，仅在镶嵌开口内，其中第一金属层形成底部电极，电介质层形成电容器 电介质，并且第二金属层形成顶部电极，以在集成电路器件的制造中完成冠型电容器的制造。

公开(公告)号：US06426250B1

公开(公告)日：2002-07-30

申请号：US09863225

申请日：2001-05-24

申请人： Tzyh-Cheang Lee ,  Shyh-Chyi Wong ,  Chih-Hsien Lin ,  Chi-Feng Huang

发明人： Tzyh-Cheang Lee ,  Shyh-Chyi Wong ,  Chih-Hsien Lin ,  Chi-Feng Huang

IPC分类号： H01L218242

CPC分类号： H01L28/90 ,  Y10S438/957

摘要： A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.

摘要翻译： 在第一电介质层中形成第一金属插头。 产生独立的第二金属插头，其与第一金属插头对准并与第一金属插头接触，延伸第一金属插头。 第二个金属插塞由已经在蚀刻停止层和电介质层上形成的开口围绕。 电容器电介质层沉积在第一和第二金属插头的暴露表面和围绕第二插头的开口的内表面中。 在蚀刻停止层和电介质层的开口内部的电容器电介质上形成一层金属。

公开(公告)号：US20050132549A1

公开(公告)日：2005-06-23

申请号：US10853459

申请日：2004-05-25

申请人： Wong-Cheng Shih ,  Wen-Chi Ting ,  Tzyh-Cheang Lee ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

发明人： Wong-Cheng Shih ,  Wen-Chi Ting ,  Tzyh-Cheang Lee ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

IPC分类号： H01L21/02 ,  H01L21/316 ,  H01G9/00

CPC分类号： H01L28/40 ,  H01L21/31604 ,  H01L28/56 ,  Y10T29/43 ,  Y10T29/435

摘要： A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.

摘要翻译： 实现了制造具有高介电常数绝缘体并夹在宽带隙绝缘体之间的金属绝缘体金属（MIM）电容器的方法，导致低漏电流和每单位面积的高电容。 高k层增加下一代混合信号器件的单位面积电容，而宽带绝缘子减少泄漏电流。 在第二实施例中，在宽带绝缘体之间形成不同的高k材料的多层以大大增加每单位面积的电容。 优化了层材料和厚度，以减少非线性电容对电压的依赖性。

公开(公告)号：US06559493B2

公开(公告)日：2003-05-06

申请号：US10167864

申请日：2002-06-11

申请人： Tzyh-Cheang Lee ,  Shyh-Chyi Wong ,  Chih-Hsien Lin ,  Chi-Feng Huang

发明人： Tzyh-Cheang Lee ,  Shyh-Chyi Wong ,  Chih-Hsien Lin ,  Chi-Feng Huang

IPC分类号： H01L31119

CPC分类号： H01L28/90 ,  Y10S438/957

摘要： A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.

摘要翻译： 在第一电介质层中形成第一金属插头。 产生独立的第二金属插头，其与第一金属插头对准并与第一金属插头接触，延伸第一金属插头。 第二个金属插塞由已经在蚀刻停止层和电介质层上形成的开口围绕。 电容器电介质层沉积在第一和第二金属插头的暴露表面和围绕第二插头的开口的内表面中。 在蚀刻停止层和电介质层的开口内部的电容器电介质上形成一层金属。

公开(公告)号：US20090213940A1

公开(公告)日：2009-08-27

申请号：US12110570

申请日：2008-04-28

申请人： Eckehard Goetz Steinbach ,  Wei-Kung Deng ,  Shyh-Chyi Wong

发明人： Eckehard Goetz Steinbach ,  Wei-Kung Deng ,  Shyh-Chyi Wong

IPC分类号： H04N7/26

CPC分类号： H04N19/895 ,  H04N19/124 ,  H04N19/132 ,  H04N19/166 ,  H04N19/176

摘要： Systems and methods for delivering real-time video imagery to a receiver over a channel. A current video frame is captured and digitized. The digitized frame is divided into a plurality of macroblocks. For each macroblock an intra, inter or skip mode coding mode is determined. Based on instantaneous feedback received from a receiver regarding successfully received video packets for a prior video frame, a quantization parameter is set and the macroblocks are encoded in accordance with their respective selected coding mode. Synchronized error concealment is performed at both the encoder and decoder sides of the system and retransmission of lost video packets, using an adaptive retransmission scheme, are performed in accordance with the instantaneous feedback from the receiver.

摘要翻译： 通过频道将实时视频图像传送到接收器的系统和方法。 当前的视频帧被捕获并数字化。 数字化帧被分成多个宏块。 对于每个宏块，确定帧内，帧间或跳过模式编码模式。 基于从接收机接收到的关于先前视频帧的成功接收的视频分组的瞬时反馈，设置量化参数，并且根据它们各自选择的编码模式对宏块进行编码。 在系统的编码器和解码器侧执行同步错误隐藏，并且根据来自接收机的瞬时反馈来执行使用自适应重传方案的丢失视频分组的重传。

公开(公告)号：US07061056B2

公开(公告)日：2006-06-13

申请号：US10623907

申请日：2003-07-18

申请人： Chao-Chieh Tsai ,  Shyh-Chyi Wong ,  Chung-Long Chang

发明人： Chao-Chieh Tsai ,  Shyh-Chyi Wong ,  Chung-Long Chang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28114 ,  H01L21/76819 ,  H01L21/76895 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/665

摘要： A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET. Whereby the width of the metal gate portion reduces Rg and increases the fMAX of the high fMAX deep submicron MOSFET.

摘要翻译： 一种形成高密度亚微米级MOSFET的方法，包括以下步骤。 提供其上形成有MOSFET的衬底。 MOSFET具有源极和漏极，并且在栅极上方包括硅化物部分。 在衬底和MOSFET上形成第一ILD层。 将第一ILD层平坦化以在栅电极上露出硅化物部分。 金属栅极部分形成在平坦化的第一ILD层之上并且在栅电极上方的硅化物部分之上。 金属栅极部分的宽度基本上大于栅电极上的硅化物部分的宽度。 第二ILD层形成在金属栅极部分和第一ILD层上。 通过与金属栅极部分接触的第二ILD层形成第一金属触点，并且通过接触漏极的第二和第一ILD层形成第二金属触点，从而形成高的最大深度 亚微米MOSFET。 由此金属栅极部分的宽度减小R＆lt;＆gt;并增加高的最大深亚微米MOSFET的最大最大值。

公开(公告)号：US06845347B1

公开(公告)日：2005-01-18

申请号：US09621698

申请日：2000-07-21

申请人： Shih Hsien Yang ,  Shyh-Chyi Wong

发明人： Shih Hsien Yang ,  Shyh-Chyi Wong

IPC分类号： G06F7/60 ,  G06F17/10 ,  G06F17/50 ,  G11C11/00

CPC分类号： G06F17/5036

摘要： Method and apparatus determine the performance of an integrated circuit that includes at least one of a plurality of deep-well trench dynamic random-access memory (DRAM) cells. The method includes executing a circuit simulator for designing an integrated circuit that contains at least one of a plurality of DRAM cells. Further, the method includes calculating a set of output parameters with the circuit simulator for each of the plurality of DRAM cells utilizing, for example, a deep-well trench DRAM cell model for each of the plurality of DRAM cells.

摘要翻译： 方法和装置确定包括多个深阱沟槽动态随机存取存储器（DRAM）单元中的至少一个的集成电路的性能。 该方法包括执行用于设计包含多个DRAM单元中的至少一个的集成电路的电路模拟器。 此外，该方法包括利用例如用于多个DRAM单元中的每个DRAM单元的深井沟槽DRAM单元模型，利用电路模拟器为多个DRAM单元中的每一个单元计算一组输出参数。

公开(公告)号：US6124618A

公开(公告)日：2000-09-26

申请号：US379281

申请日：1999-08-23

申请人： Shyh-Chyi Wong ,  Mong-Song Liang

发明人： Shyh-Chyi Wong ,  Mong-Song Liang

IPC分类号： H01L27/06 ,  H01L27/12 ,  H01L29/72

CPC分类号： H01L27/0635 ,  H01L27/1203

摘要： A dynamic threshold voltage MOSFET to provide increase drain-to-source saturation current (I.sub.DSsat) and lower off current (I.sub.off) is described. The dynamic threshold voltage MOSFET has a first diffusion-well of a material of a first conductivity type formed at the surface of the substrate to form a bulk region. A source region and a drain region of a material of a second conductivity type are diffused into the diffusion-well. A first gate is then placed on a first oxide surface above the substrate between the source and drain regions. An accumulated base bipolar transistor is then placed on the semiconductor substrate. The base of the accumulated base bipolar transistor is connected to the gate, the emitter is connected to the diffusion-well. A resistor is connected between the emitter of the accumulated base bipolar transistor and a substrate biasing voltage source. A biasing circuit connected to the collector of the accumulated base bipolar transistor to provide a bias voltage for the accumulated base bipolar transistor.

摘要翻译： 描述了提供增加漏极 - 源极饱和电流（IDSsat）和降低截止电流（Ioff）的动态阈值电压MOSFET。 动态阈值电压MOSFET具有在衬底的表面形成的第一导电类型的材料的第一扩散阱，以形成体积区域。 第二导电类型的材料的源极区域和漏极区域扩散到扩散井中。 然后将第一栅极放置在源极和漏极区域之间的衬底上方的第一氧化物表面上。 然后将积累的基极双极晶体管放置在半导体衬底上。 累积的基极双极晶体管的基极连接到栅极，发射极连接到扩散井。 一个电阻连接在累积的基极双极晶体管的发射极和一个衬底偏置电压源之间。 连接到累积的基极双极晶体管的集电极的偏置电路，为累积的基极双极晶体管提供偏置电压。