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    Carry circuit suitable for a high-speed arithmetic operation
    1.
    发明授权
    Carry circuit suitable for a high-speed arithmetic operation 失效
    携带电路适用于高速算术运算

    公开(公告)号：US4845655A

    公开(公告)日：1989-07-04

    申请号：US164032

    申请日：1988-03-04

    申请人： Kouichi Yamada ,  Masatoshi Mizuno

    发明人： Kouichi Yamada ,  Masatoshi Mizuno

    IPC分类号： G06F7/50 ,  G06F7/507

    CPC分类号： G06F7/507

    摘要： A carry circuit used in an arithmetic unit, such as an adder or a subtractor, has to process a carry operation for producing a carry signal to be transferred to the following carry operation stage according to a carry signal transferred from the previous carry operation stage. To process this carry operation at a high speed, an improved carry circuit performs two operations before the carry signal from the previous stage is received. One of the operations is processed by using a signal representing that the carry signal from the previous stage is present. The other operation is processed by using another signal representing that the carry signal from the previous stage is absent. These two operations have been terminated when the carry signal from the previous stage is received. The carry signal from the previous stage is used to select either one of results of the two operations. Thus, transmission of a carry signal to the following stage can be performed at a high speed.

    Carry circuit suitable for a high-speed arithmetic operation
    2.
    发明授权
    Carry circuit suitable for a high-speed arithmetic operation 失效
    携带电路适用于高速算术运算

    公开(公告)号：US4763295A

    公开(公告)日：1988-08-09

    申请号：US686802

    申请日：1984-12-27

    申请人： Kouichi Yamada ,  Masatoshi Mizuno

    发明人： Kouichi Yamada ,  Masatoshi Mizuno

    IPC分类号： G06F7/50 ,  G06F7/507

    CPC分类号： G06F7/507

    摘要： A carry circuit used in an arithmetic unit, such as an adder or a subtractor, has to process a carry operation for producing a carry signal to be transferred to the following carry operation stage according to a carry signal transferred from the previous carry operation stage. To process this carry operation at a high speed, an improved carry circuit performs two operations before the carry signal from the previous stage is received. One of the operations is processed by using a signal representing that the carry signal from the previous stage is present. The other operation is processed by using another signal representing that the carry signal from the previous stage is absent. These two operations have been terminated when the carry signal from the previous stage is received. The carry signal from the previous stage is used to select either one of results of the two operations. Thus, transmission of a carry signal to the following stage can be performed at a high speed.

    摘要翻译： 用于诸如加法器或减法器之类的算术单元中的进位电路必须根据从先前进位操作级传送的进位信号，处理用于产生要传送到后续进位运算级的进位信号的进位运算。 为了高速处理该进位操作，在接收到来自前一级的进位信号之前，改进的进位电路执行两个操作。 通过使用表示来自前一级的进位信号的信号来处理其中一个操作。 通过使用表示来自前一级的进位信号不存在的另一个信号来处理另一个操作。 当接收到来自前一级的进位信号时，这两个操作已被终止。 来自前一级的进位信号用于选择两个操作的结果之一。 因此，可以高速进行进位信号到后一级的传输。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08507994B2

    公开(公告)日：2013-08-13

    申请号：US13205314

    申请日：2011-08-08

    申请人： Kouichi Yamada

    发明人： Kouichi Yamada

    IPC分类号： H01L27/10

    CPC分类号： G11C5/063 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

    摘要： In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.

    摘要翻译： 在包括CMOS反相器的存储单元中，由于漏电流引起的栅极布线的限制和由于设计规则的限制而导致的存储单元面积的增加被抑制。 在包括第一反相器和第二反相器的存储单元中布置第一布线和第二布线作为第一金属层。 第一布线连接在第一反相器中的两个漏极和第二反相器中的第二栅极布线。 第二布线与第二反相器中的两个漏极和第一反相器中的第一栅极布线连接。 第一布线布置成与第二栅极布线重叠，并且布置第二布线以与第一栅极布线重叠。 第二金属层布置在第一金属层上方，第三金属层布置在第二金属层的上方。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110186935A1

    公开(公告)日：2011-08-04

    申请号：US13016481

    申请日：2011-01-28

    申请人： Yoshitaka UEDA ,  Kouichi Yamada ,  Atsushi Wada ,  Shigeto Kobayashi

    发明人： Yoshitaka UEDA ,  Kouichi Yamada ,  Atsushi Wada ,  Shigeto Kobayashi

    IPC分类号： H01L27/105

    CPC分类号： H01L27/105

    摘要： A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.

    摘要翻译： MOS晶体管包括形成为栅格图案的栅极电极，由栅电极围绕的源极区域和漏极区域以及经由源极触点连接到源极区域的源极金属布线和经由漏极连接到漏极区域的漏极金属布线 联系人 源金属布线和漏极金属布线沿着栅电极的栅格的一个方向设置。 源极区域和漏极区域中的每一个是沿着每个金属布线的长度方向具有长边的矩形形状。 源极金属布线和漏极金属布线分别在长度方向上以锯齿形形式分别连接到源极触点和漏极触点。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07474570B2

    公开(公告)日：2009-01-06

    申请号：US11247153

    申请日：2005-10-12

    申请人： Kouichi Yamada

    发明人： Kouichi Yamada

    IPC分类号： G11C7/00

    CPC分类号： G11C11/22 ,  G11C7/08 ,  G11C11/4091

    摘要： A semiconductor device capable of improving the accuracy determines whether a prescribed input potential is higher or lower than a reference potential. This semiconductor device comprises first capacitance unit and second capacitance unit having different ON- and OFF-state capacitances. The semiconductor device changes the potential of a first electrode of the first capacitance unit and the potential of a first electrode of the second capacitance unit from a first potential to a second potential thereby enlarging the difference between a potential input in a second electrode of the first capacitance unit and a potential input in a second electrode of the second capacitance unit and comparing the potential input in the second electrode of the first capacitance unit and the potential input in the second electrode of the second capacitance unit with each other.

    摘要翻译： 能够提高精度的半导体装置决定规定的输入电位是高于还是低于参考电位。 该半导体器件包括具有不同导通和截止状态电容的第一电容单元和第二电容单元。 半导体器件将第一电容单元的第一电极的电位和第二电容单元的第一电极的电位从第一电位改变为第二电位，从而扩大第一电容的第二电极中的电位输入之间的差 电容单元和第二电容单元的第二电极中的电位输入，并将第一电容单元的第二电极中的电位输入与第二电容单元的第二电极中的电位输入进行比较。

    Memory
    8.
    发明申请
    Memory 有权
    记忆

    公开(公告)号：US20070242542A1

    公开(公告)日：2007-10-18

    申请号：US11727687

    申请日：2007-03-28

    申请人： Kouichi Yamada

    发明人： Kouichi Yamada

    IPC分类号： G11C7/02

    CPC分类号： G11C17/10

    摘要： A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.

    摘要翻译： 获得可高速操作的存储器。 该存储器包括多个字线，每个连接到多个字线中的每一个用于通过选择相应的字线来进入导通状态的第一晶体管，多个存储单元包括具有连接到源极或漏极区域的阴极的二极管 的第一晶体管的漏极或源极区域连接的数据确定部分，用于确定从所选存储器单元读取的数据。

    Memory
    9.
    发明申请
    Memory 有权
    记忆

    公开(公告)号：US20070237016A1

    公开(公告)日：2007-10-11

    申请号：US11630851

    申请日：2005-06-16

    申请人： Hideaki Miyamoto ,  Naofumi Sakai ,  Kouichi Yamada ,  Shigeharu Matsushita

    发明人： Hideaki Miyamoto ,  Naofumi Sakai ,  Kouichi Yamada ,  Shigeharu Matsushita

    IPC分类号： G11C7/00

    CPC分类号： G11C11/22

    摘要： A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array(1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells(12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell(12). During this access operation, it is performed to apply to the memory cell(12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell(12).

    摘要翻译： 可以抑制其中未选择的存储单元中的数据丢失的任何“干扰效应”的存储器。 该存储器具有存储单元阵列（1），该存储单元阵列（1）包括位线，设置成与位线相交的字线以及每个连接在位线和字线之间的存储单元（12）。 在该存储器中，对选择的存储器单元（12）进行包括读取，重写和写入操作中的至少一个的访问操作。 在该访问操作期间，执行向存储器单元（12）施加第一电压脉冲，该第一电压脉冲在第一方向上提供电场以反转存储的数据，以及第二电压脉冲，其提供为电场 与第一个方向相反的方向，以便不反转存储的数据。 此外，对存储单元（12）进行用于恢复残留极化量的恢复操作。

    Digital broadcast receiving apparatus
    10.
    发明授权
    Digital broadcast receiving apparatus 有权
    数字广播接收装置

    公开(公告)号：US07248304B2

    公开(公告)日：2007-07-24

    申请号：US11337517

    申请日：2006-01-24

    申请人： Shigeyuki Okada ,  Kouichi Yamada ,  Mamoru Mukuno

    发明人： Shigeyuki Okada ,  Kouichi Yamada ,  Mamoru Mukuno

    IPC分类号： H04N5/50

    CPC分类号： H04N21/4383 ,  H04N5/4401 ,  H04N21/4263 ,  H04N21/433 ,  H04N21/4382 ,  H04N21/44016 ,  H04N21/44209 ,  H04N21/4435

    摘要： The digital broadcast receiving apparatus according to the present invention includes a tuning unit for outputting normal image data for performing a normal reproduction operation corresponding to a user selected channel, a memory unit for outputting background image data for performing a background reproduction operation when the normal reproduction operation cannot be performed, a data selector for receiving the normal image data and the background image data and outputting one of the normal image data and the background image data, and an MPEG video decode unit for decoding image data output by the data selector to generate an image signal. The tuning unit successively receives the respective channel selected in the background independently of the user selection, and stores the background image data corresponding to the respective channels in the memory unit.

    摘要翻译： 根据本发明的数字广播接收装置包括：调谐单元，用于输出用于执行与用户选择的频道相对应的正常再现操作的正常图像数据;存储单元，用于输出当正常再现时执行背景再现操作的背景图像数据 无法执行操作的数据选择器，用于接收正常图像数据和背景图像数据并输出正常图像数据和背景图像数据之一的数据选择器，以及用于解码由数据选择器输出的图像数据的MPEG视频解码单元，以产生 图像信号。 调谐单元连续地接收与用户选择无关地在背景中选择的相应频道，并且将与各个频道相对应的背景图像数据存储在存储单元中。