公开(公告)号：US20070244948A1

公开(公告)日：2007-10-18

申请号：US11392471

申请日：2006-03-28

Applicant: Kuljit Bains ,  John Halbert ,  Greg Lemos ,  Randy Osborne

Inventor： Kuljit Bains ,  John Halbert ,  Greg Lemos ,  Randy Osborne

IPC: G06F7/78

CPC classification number: G06F13/1678

Abstract: In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，数据可以以具有第一宽度的第一格式从第一存储器传送到第二存储器代理，并且数据的至少关键部分可以从第二存储器代理返回到第一存储器 具有第二宽度的第二格式，其中临界部分包括在第一帧中。 关键部分可以包括在存储器设备等级上映射的高速缓存线。 描述和要求保护其他实施例。

公开(公告)号：US20050138267A1

公开(公告)日：2005-06-23

申请号：US10746948

申请日：2003-12-23

Applicant: Kuljit Bains ,  Robert Ellis ,  Chris Freeman ,  John Halbert ,  Michael Williams

Inventor： Kuljit Bains ,  Robert Ellis ,  Chris Freeman ,  John Halbert ,  Michael Williams

IPC: G11C5/00 ,  G11C7/10 ,  G11C7/20 ,  G06F12/16

CPC classification number: G11C7/1051 ,  G06F13/1673 ,  G06F13/1684 ,  G11C7/1078 ,  G11C7/20

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, a serial presence detect function is included within a memory module buffer instead of being provided by a separate EEPROM device mounted on the memory module. Various embodiments thus can provide cost savings, chip placement and signal routing simplification, and can in some circumstances save pins on the module. Other embodiments are described and claimed.

Abstract translation: 在实施例中包括用于缓冲存储器模块的方法和装置。 在示例性系统中，串行存在检测功能被包括在存储器模块缓冲器内，而不是由安装在存储器模块上的单独的EEPROM器件提供。 因此，各种实施例可以提供成本节省，芯片放置和信号路由简化，并且在某些情况下可以在模块上保存引脚。 描述和要求保护其他实施例。

公开(公告)号：US20050071543A1

公开(公告)日：2005-03-31

申请号：US10674981

申请日：2003-09-29

Applicant: Robert Ellis ,  Kuljit Bains ,  Chris Freeman ,  John Halbert ,  Narendra Khandekar ,  Michael Williams

Inventor： Robert Ellis ,  Kuljit Bains ,  Chris Freeman ,  John Halbert ,  Narendra Khandekar ,  Michael Williams

IPC: G06F13/16 ,  G11C5/00 ,  G11C11/406 ,  G06F12/00

CPC classification number: G11C11/406 ,  G06F13/1636 ,  G11C2211/4061

Abstract: Apparatus and method to carry out refresh operations on rows of memory cells within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

Abstract translation: 在存储器总线上没有活动的情况下，独立于存储器控制器，在与存储器件相关联的存储器控​​制器的存储器总线的时间内，独立于存储器控制器，在存储器件中的行存储器单元上执行刷新操作的装置和方法。

公开(公告)号：US09117544B2

公开(公告)日：2015-08-25

申请号：US14068677

申请日：2013-10-31

Applicant: Kuljit Bains ,  John Halbert ,  Christopher Mozak ,  Theodore Schoenborn ,  Zvika Greenfield

Inventor： Kuljit Bains ,  John Halbert ,  Christopher Mozak ,  Theodore Schoenborn ,  Zvika Greenfield

IPC: G06F13/10 ,  G11C11/406 ,  G11C7/02

CPC classification number: G11C11/40615 ,  G11C7/02 ,  G11C11/40611 ,  G11C11/40622

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract translation: 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值（也称为“锤击”或“行锤事件”）中重复访问时，物理上相邻的行（“受害者”行）可能会遭遇数据损坏。 存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

公开(公告)号：US20150109871A1

公开(公告)日：2015-04-23

申请号：US14108830

申请日：2013-12-17

Applicant: Kuljit BAINS ,  John Halbert

Inventor： Kuljit BAINS ,  John Halbert

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to it row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract translation: 存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内的数量的访问，导致物理上相邻的行上的数据损坏风险。 检测逻辑从存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目 。 检测逻辑确定存储器件的行的访问次数是否超过阈值。 响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器件执行针对物理上相邻的受害者行的刷新。

公开(公告)号：US20050144375A1

公开(公告)日：2005-06-30

申请号：US10750154

申请日：2003-12-31

Applicant: Kuljit Bains ,  John Halbert ,  Randy Osborne

Inventor： Kuljit Bains ,  John Halbert ,  Randy Osborne

IPC: G06F12/00 ,  G06F13/16

CPC classification number: G06F13/161

Abstract: Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.

Abstract translation: 具有存储单元组的存储器单元被组织成共享控制电路的两组存储体，以及数据缓冲器以提供与存储器总线的接口，但它们独立地可操作以足以支持与每个组的无关交易，并且可以用于交错 以缩短的突发传输进行读操作，以最大限度地减少内存总线上的死区时间。

公开(公告)号：US20070150667A1

公开(公告)日：2007-06-28

申请号：US11317757

申请日：2005-12-23

Applicant: Kuljit Bains ,  John Halbert ,  Randy Osborne

Inventor： Kuljit Bains ,  John Halbert ,  Randy Osborne

IPC: G06F13/28

CPC classification number: G06F13/1684

Abstract: In some embodiments, a chip includes first and second bank sets, a first data port mapped to the first bank set, and a second data port mapped to the second bank set. Other embodiments are described.

Abstract translation: 在一些实施例中，芯片包括第一和第二组组，映射到第一组组的第一数据端口和映射到第二组组的第二数据端口。 描述其他实施例。

公开(公告)号：US20050146975A1

公开(公告)日：2005-07-07

申请号：US10750038

申请日：2003-12-30

Applicant: John Halbert ,  Robert Ellis ,  Kuljit Bains ,  Chris Freeman

Inventor： John Halbert ,  Robert Ellis ,  Kuljit Bains ,  Chris Freeman

IPC: G11C7/10 ,  G11C11/4096 ,  G11C8/00

CPC classification number: G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4096 ,  G11C2207/005

Abstract: Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.

Abstract translation: 提供和使用隔离器组，以使得能够通过与子阵列相关联的一行读出放大器将存储器件组的子阵列内的至少一行存储器单元的内容缓存以使得能够更快地访问内容 通过读取操作使至少一行直接从存储器单元行读取数据从读出放大器行读取。

公开(公告)号：US20050081085A1

公开(公告)日：2005-04-14

申请号：US10674320

申请日：2003-09-29

Applicant: Robert Ellis ,  Kuljit Bains ,  Chris Freeman ,  John Halbert

Inventor： Robert Ellis ,  Kuljit Bains ,  Chris Freeman ,  John Halbert

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1044

Abstract: Apparatus and method to carry out checks for memory errors within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

Abstract translation: 在存储器总线上没有活动的情况下，与存储器控制器独立地对存储器件内的存储器错误执行检查的装置和方法，该存储器总线将存储器装置耦合到涉及存储器件的存储器控​​制器。

公开(公告)号：US20060117129A1

公开(公告)日：2006-06-01

申请号：US11329994

申请日：2006-01-10

Applicant: Kuljit Bains ,  Herbert Hum ,  John Halbert

Inventor： Kuljit Bains ,  Herbert Hum ,  John Halbert

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0864 ,  G06F12/0882

Abstract: A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.