公开(公告)号：US07928512B2

公开(公告)日：2011-04-19

申请号：US11776562

申请日：2007-07-12

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Lang

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Lang

IPC分类号： H01L27/12

CPC分类号： H01L21/823412 ,  H01L21/823468 ,  H01L29/7842

摘要： A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.

摘要翻译： 本文提供了一种半导体器件，其包括具有第一型MOS晶体管，形成在其上的输入/输出（I / O）第二型MOS晶体管和核心第二型MOS晶体管的衬底。 半导体器件还包括第一应力层和第二应力层。 第一应力层设置在第一型MOS晶体管上或第一型MOS晶体管和I / O第二型MOS晶体管上。 第二应力层设置在芯型二次型MOS晶体管上。

公开(公告)号：US20080206942A1

公开(公告)日：2008-08-28

申请号：US11678627

申请日：2007-02-26

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

摘要翻译： 公开了制造应变硅晶体管的方法。 首先，提供半导体衬底，并且在半导体衬底上设置栅极结构和围绕栅极结构的间隔物。 然后在隔离物周围的半导体衬底中形成源极/漏极区域，并且执行第一快速热退火处理以激活源极/漏极区域内的掺杂剂。 执行蚀刻工艺以在栅极结构周围形成凹陷，并且执行选择性外延生长工艺以在凹部中形成外延层。 执行第二快速热退火处理以重新定义源/漏区域内的掺杂剂的分布并修复掺杂剂的损坏的键。

公开(公告)号：US20080020588A1

公开(公告)日：2008-01-24

申请号：US11459008

申请日：2006-07-20

申请人： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Liang ,  Neng-Kuo Chen

发明人： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Liang ,  Neng-Kuo Chen

IPC分类号： H01L21/31

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.

摘要翻译： 一种形成半导体器件的方法。 该方法包括以下步骤：提供具有形成在其上的第一晶体管，第二晶体管和非自对准硅化物器件的衬底，并且第一晶体管的导电类型与第二晶体管的导电类型不同。 在衬底上形成缓冲层，并在缓冲层上形成拉伸材料层。 第二晶体管上的拉伸材料层的一部分变薄，并且执行尖峰退火处理。 除去拉伸材料层以暴露衬底上的缓冲层，并且在非自对准硅化物器件上形成图案化的自对准硅化物阻挡层。 执行自对准处理以在第一晶体管和第二晶体管的一部分上形成自对准硅化物层。

公开(公告)号：US20080020523A1

公开(公告)日：2008-01-24

申请号：US11490210

申请日：2006-07-19

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Jing-Yi Huang ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Jing-Yi Huang ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823864 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/82385

摘要： A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.

摘要翻译： 提供一种制造金属氧化物半导体晶体管的方法。 在基板上形成第一栅极结构和第二栅极结构。 第一栅极结构的尺寸大于第二栅极结构。 然后，在第一栅极结构的两侧的基板中形成第一轻掺杂漏极区。 进行轻掺杂的漏极退火处理。 接下来，在第二栅极结构的两侧的基板中形成第二轻掺杂漏极区。 第一间隔件形成在第一栅极结构的侧壁上，并且第二间隔件同时形成在第二栅极结构的侧壁上。 之后，第一源极/漏极区域形成在第一间隔物的两侧的衬底中，并且第二源极/漏极区域形成在第二间隔物的两侧上的衬底中。 进行源/漏退火处理。

公开(公告)号：US07288822B1

公开(公告)日：2007-10-30

申请号：US11399827

申请日：2006-04-07

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the lattice parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the lattice parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

摘要翻译： 公开了一种半导体结构，包括其中具有第一导电类型的第一阱和第二导电类型的第二阱的衬底，第一导电类型的第一MOS晶体管和第二导电类型的第二MOS晶体管。 第一MOS晶体管设置在第二阱上，包括在第二阱上的栅极结构和位于栅极结构旁边的第二阱中的开口中的第一导电类型的应变层。 开口底部附近的应变层的一部分的晶格参数与基板的晶格参数之间的差异小于开口底部以外的应变层的一部分的晶格参数之间的差异， 底物。 第二MOS晶体管设置在第一阱上。

公开(公告)号：US20110254064A1

公开(公告)日：2011-10-20

申请号：US13171579

申请日：2011-06-29

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng

IPC分类号： H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： An exemplary semiconductor device includes a substrate, a spacer, a metal silicide layer and carbon atoms. The substrate has a gate structure formed thereon. The spacer is formed on the sidewall of the gate structure. The spacer has a first side adjacent to the gate structure and a second side away from the gate structure. The metal silicide layer is formed on the substrate and adjacent to the second side of the spacer but away from the first side of the spacer. The carbon atoms are formed into the substrate and adjacent to the first side of the spacer but away from the second side of the spacer.

摘要翻译： 示例性的半导体器件包括衬底，间隔物，金属硅化物层和碳原子。 基板上形成有栅极结构。 间隔件形成在栅极结构的侧壁上。 间隔件具有与栅极结构相邻的第一侧和远离栅极结构的第二侧。 金属硅化物层形成在衬底上并且邻近间隔物的第二侧而远离间隔物的第一侧。 碳原子形成在衬底中并且邻近间隔物的第一侧而远离间隔物的第二侧。

公开(公告)号：US07927954B2

公开(公告)日：2011-04-19

申请号：US11678627

申请日：2007-02-26

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

摘要翻译： 公开了制造应变硅晶体管的方法。 首先，提供半导体衬底，并且在半导体衬底上设置栅极结构和围绕栅极结构的间隔物。 然后在隔离物周围的半导体衬底中形成源极/漏极区域，并且执行第一快速热退火处理以激活源极/漏极区域内的掺杂剂。 执行蚀刻工艺以在栅极结构周围形成凹陷，并且执行选择性外延生长工艺以在凹部中形成外延层。 执行第二快速热退火处理以重新定义源/漏区域内的掺杂剂的分布并修复掺杂剂的损坏的键。

公开(公告)号：US07888223B2

公开(公告)日：2011-02-15

申请号：US11692609

申请日：2007-03-28

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Meng-Yi Wu ,  Tzyy-Ming Cheng

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659

摘要： A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

摘要翻译： 制造p型沟道FET的方法包括在衬底上形成栅极。 然后，执行PAI离子注入工艺。 此外，进行袋注入工艺以形成袋区域。 此后，执行第一共注入工艺以限定源极/漏极延伸区域深度分布。 然后，形成p型源极/漏极延伸区域。 之后，执行第二共注入处理以限定源极/漏极区域深度分布。 此后，进行原位掺杂外延生长工艺以形成用作p型源/漏区的掺杂半导体化合物。

公开(公告)号：US07582520B2

公开(公告)日：2009-09-01

申请号：US11490210

申请日：2006-07-19

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Jing-Yi Huang ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Jing-Yi Huang ,  Tzyy-Ming Cheng ,  Chia-Wen Liang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823864 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/82385

摘要： A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.

摘要翻译： 提供一种制造金属氧化物半导体晶体管的方法。 在基板上形成第一栅极结构和第二栅极结构。 第一栅极结构的尺寸大于第二栅极结构。 然后，在第一栅极结构的两侧的基板中形成第一轻掺杂漏极区。 进行轻掺杂的漏极退火处理。 接下来，在第二栅极结构的两侧上的基板中形成第二轻掺杂漏极区。 第一间隔件形成在第一栅极结构的侧壁上，并且第二间隔件同时形成在第二栅极结构的侧壁上。 之后，第一源极/漏极区域形成在第一间隔物的两侧的衬底中，并且第二源极/漏极区域形成在第二间隔物的两侧上的衬底中。 进行源/漏退火处理。

公开(公告)号：US20090117701A1

公开(公告)日：2009-05-07

申请号：US11934053

申请日：2007-11-01

申请人： Meng-Yi Wu ,  Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Chung-Min Shih ,  Yao-Chin Cheng ,  Tzyy-Ming Cheng

发明人： Meng-Yi Wu ,  Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Chung-Min Shih ,  Yao-Chin Cheng ,  Tzyy-Ming Cheng

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/28247

摘要： A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility.

摘要翻译： 制造MOS晶体管的方法包括在形成源极/漏极延伸区域之前执行热处理以修复损坏的衬底，因此减小了负偏压温度不稳定性（NBTI）。 由于在形成源极/漏极延伸区域之前进行热处理，因此不会影响用于形成源极/漏极延伸区域的热量预算和源极/漏极延伸部的结深度和结型材。 因此，所提供的制造MOS晶体管的方法能够减少短沟道效应并具有优异的工艺兼容性。