Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US07928512B2

    公开(公告)日:2011-04-19

    申请号:US11776562

    申请日:2007-07-12

    IPC分类号: H01L27/12

    摘要: A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.

    摘要翻译: 本文提供了一种半导体器件,其包括具有第一型MOS晶体管,形成在其上的输入/输出(I / O)第二型MOS晶体管和核心第二型MOS晶体管的衬底。 半导体器件还包括第一应力层和第二应力层。 第一应力层设置在第一型MOS晶体管上或第一型MOS晶体管和I / O第二型MOS晶体管上。 第二应力层设置在芯型二次型MOS晶体管上。

    METHOD FOR FORMING SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号:US20080020588A1

    公开(公告)日:2008-01-24

    申请号:US11459008

    申请日:2006-07-20

    IPC分类号: H01L21/31

    摘要: A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.

    摘要翻译: 一种形成半导体器件的方法。 该方法包括以下步骤:提供具有形成在其上的第一晶体管,第二晶体管和非自对准硅化物器件的衬底,并且第一晶体管的导电类型与第二晶体管的导电类型不同。 在衬底上形成缓冲层,并在缓冲层上形成拉伸材料层。 第二晶体管上的拉伸材料层的一部分变薄,并且执行尖峰退火处理。 除去拉伸材料层以暴露衬底上的缓冲层,并且在非自对准硅化物器件上形成图案化的自对准硅化物阻挡层。 执行自对准处理以在第一晶体管和第二晶体管的一部分上形成自对准硅化物层。

    Method of fabricating complementary metal-oxide-semiconductor transistor and metal-oxide-semiconductor transistor
    4.
    发明申请
    Method of fabricating complementary metal-oxide-semiconductor transistor and metal-oxide-semiconductor transistor 有权
    互补金属氧化物半导体晶体管和金属氧化物半导体晶体管的制造方法

    公开(公告)号:US20080020523A1

    公开(公告)日:2008-01-24

    申请号:US11490210

    申请日:2006-07-19

    IPC分类号: H01L21/8234

    摘要: A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.

    摘要翻译: 提供一种制造金属氧化物半导体晶体管的方法。 在基板上形成第一栅极结构和第二栅极结构。 第一栅极结构的尺寸大于第二栅极结构。 然后,在第一栅极结构的两侧的基板中形成第一轻掺杂漏极区。 进行轻掺杂的漏极退火处理。 接下来,在第二栅极结构的两侧的基板中形成第二轻掺杂漏极区。 第一间隔件形成在第一栅极结构的侧壁上,并且第二间隔件同时形成在第二栅极结构的侧壁上。 之后,第一源极/漏极区域形成在第一间隔物的两侧的衬底中,并且第二源极/漏极区域形成在第二间隔物的两侧上的衬底中。 进行源/漏退火处理。

    Semiconductor structure and fabricating method thereof
    5.
    发明授权
    Semiconductor structure and fabricating method thereof 有权
    半导体结构及其制造方法

    公开(公告)号:US07288822B1

    公开(公告)日:2007-10-30

    申请号:US11399827

    申请日:2006-04-07

    摘要: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the lattice parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the lattice parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

    摘要翻译: 公开了一种半导体结构,包括其中具有第一导电类型的第一阱和第二导电类型的第二阱的衬底,第一导电类型的第一MOS晶体管和第二导电类型的第二MOS晶体管。 第一MOS晶体管设置在第二阱上,包括在第二阱上的栅极结构和位于栅极结构旁边的第二阱中的开口中的第一导电类型的应变层。 开口底部附近的应变层的一部分的晶格参数与基板的晶格参数之间的差异小于开口底部以外的应变层的一部分的晶格参数之间的差异, 底物。 第二MOS晶体管设置在第一阱上。