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    Transistor having vertical junction edge and method of manufacturing the same
    4.
    发明申请
    Transistor having vertical junction edge and method of manufacturing the same 有权
    具有垂直接合边缘的晶体管及其制造方法

    公开(公告)号：US20050145952A1

    公开(公告)日：2005-07-07

    申请号：US10751141

    申请日：2003-12-31

    申请人： Fernando Gonzalez ,  Chandra Mouli

    发明人： Fernando Gonzalez ,  Chandra Mouli

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/66636 ,  H01L21/2257 ,  H01L21/823481 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/7834

    摘要： Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the heavily doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

    摘要翻译： 用于形成诸如晶体管的器件的技术具有垂直的接合边缘。 更具体地说，在沟槽中形成浅沟槽并填充氧化物。 可以在氧化物中形成空穴，并填充有导电材料，例如重掺杂多晶硅。 在沟槽边缘处，在多晶硅和暴露的衬底之间形成垂直结，使得在热循环期间，重掺杂多晶硅将掺杂元素扩散到相邻的单晶硅中，有利地形成具有期望特性的二极管延伸。

    Field effect transistors, field effect transistor assemblies, and integrated circuitry
    5.
    发明授权
    Field effect transistors, field effect transistor assemblies, and integrated circuitry 有权
    场效应晶体管，场效应晶体管组件和集成电路

    公开(公告)号：US06693313B2

    公开(公告)日：2004-02-17

    申请号：US10300153

    申请日：2002-11-19

    申请人： Fernando Gonzalez ,  Chandra Mouli

    发明人： Fernando Gonzalez ,  Chandra Mouli

    IPC分类号： H01L2972

    CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/42372 ,  H01L29/4925 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  Y10S257/915

    摘要： The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a first layer of conductively doped semiconductive material and only one layer of conductive nitride. The integrated circuitry further comprises a second field effect transistor supported by the substrate. The second field effect transistor comprises a second transistor gate assembly which includes a second layer of conductively doped semiconductor material and at least two layers of conductive nitride. The invention also encompasses a field effect transistor assembly which includes a channel region and an insulative material along the channel region. The transistor assembly further includes a gate stack proximate the channel region. The gate stack includes a first conductive nitride layer separated from the channel region by the insulative material. The stack further includes a conductively doped semiconductive material proximate the first conductive nitride layer, and a second conductive nitride layer separated from the first conductive nitride layer by the conductively doped semiconductive material. Additionally, the invention encompasses methods of forming field effect transistors, and methods of forming integrated circuitry.

    摘要翻译： 本发明包括集成电路，其包括半导体材料衬底和由衬底支撑的第一场效应晶体管。 第一场效应晶体管包括第一晶体管栅极组件，其包括第一导电掺杂半导体材料层和仅一层导电氮化物。 集成电路还包括由衬底支撑的第二场效应晶体管。 第二场效应晶体管包括第二晶体管栅极组件，其包括导电掺杂半导体材料的第二层和至少两层导电氮化物。 本发明还包括场效应晶体管组件，其包括沟道区和沿着沟道区的绝缘材料。 晶体管组件还包括靠近沟道区的栅极堆叠。 栅极堆叠包括通过绝缘材料与沟道区分离的第一导电氮化物层。 堆叠还包括靠近第一导电氮化物层的导电掺杂半导体材料，以及通过导电掺杂的半导体材料与第一导电氮化物层分离的第二导电氮化物层。 此外，本发明包括形成场效应晶体管的方法以及形成集成电路的方法。

    Methods of forming field effect transistors and integrated circuitry
    6.
    发明授权
    Methods of forming field effect transistors and integrated circuitry 有权
    场效应晶体管和集成电路

    公开(公告)号：US06498378B1

    公开(公告)日：2002-12-24

    申请号：US09708360

    申请日：2000-11-07

    申请人： Fernando Gonzalez ,  Chandra Mouli

    发明人： Fernando Gonzalez ,  Chandra Mouli

    IPC分类号： H01L2972

    CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/42372 ,  H01L29/4925 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  Y10S257/915

    摘要： The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a first layer of conductively doped semiconductive material and only one layer of conductive nitride. The integrated circuitry further comprises a second field effect transistor supported by the substrate. The second field effect transistor comprises a second transistor gate assembly which includes a second layer of conductively doped semiconductor material and at least two layers of conductive nitride. The invention also encompasses a field effect transistor assembly which includes a channel region and an insulative material along the channel region. The transistor assembly further includes a gate stack proximate the channel region. The gate stack includes a first conductive nitride layer separated from the channel region by the insulative material. The stack further includes a conductively doped semiconductive material proximate the first conductive nitride layer, and a second conductive nitride layer separated from the first conductive nitride layer by the conductively doped semiconductive material. Additionally, the invention encompasses methods of forming field effect transistors, and methods of forming integrated circuitry.

    摘要翻译： 本发明包括集成电路，其包括半导体材料衬底和由衬底支撑的第一场效应晶体管。 第一场效应晶体管包括第一晶体管栅极组件，其包括第一导电掺杂半导体材料层和仅一层导电氮化物。 集成电路还包括由衬底支撑的第二场效应晶体管。 第二场效应晶体管包括第二晶体管栅极组件，其包括导电掺杂半导体材料的第二层和至少两层导电氮化物。 本发明还包括场效应晶体管组件，其包括沟道区和沿着沟道区的绝缘材料。 晶体管组件还包括靠近沟道区的栅极堆叠。 栅极堆叠包括通过绝缘材料与沟道区分离的第一导电氮化物层。 堆叠还包括靠近第一导电氮化物层的导电掺杂半导体材料，以及通过导电掺杂的半导体材料与第一导电氮化物层分离的第二导电氮化物层。 此外，本发明包括形成场效应晶体管的方法以及形成集成电路的方法。

    Methods of forming field effect transistors and integrated circuitry including TiN gate element
    7.
    发明授权
    Methods of forming field effect transistors and integrated circuitry including TiN gate element 有权
    形成场效应晶体管和集成电路的方法

    公开(公告)号：US06486030B2

    公开(公告)日：2002-11-26

    申请号：US09810752

    申请日：2001-03-15

    申请人： Fernando Gonzalez ,  Chandra Mouli

    发明人： Fernando Gonzalez ,  Chandra Mouli

    IPC分类号： H01L21336

    CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/42372 ,  H01L29/4925 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  Y10S257/915

    摘要： The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a first layer of conductively doped semiconductive material and only one layer of conductive nitride. The integrated circuitry further comprises a second field effect transistor supported by the substrate. The second field effect transistor comprises a second transistor gate assembly which includes a second layer of conductively doped semiconductor material and at least two layers of conductive nitride. The invention also encompasses a field effect transistor assembly which includes a channel region and an insulative material along the channel region. The transistor assembly further includes a gate stack proximate the channel region. The gate stack includes a first conductive nitride layer separated from the channel region by the insulative material. The stack further includes a conductively doped semiconductive material proximate the first conductive nitride layer, and a second conductive nitride layer separated from the first conductive nitride layer by the conductively doped semiconductive material. Additionally, the invention encompasses methods of forming field effect transistors, and methods of forming integrated circuitry.

    摘要翻译： 本发明包括集成电路，其包括半导体材料衬底和由衬底支撑的第一场效应晶体管。 第一场效应晶体管包括第一晶体管栅极组件，其包括第一导电掺杂半导体材料层和仅一层导电氮化物。 集成电路还包括由衬底支撑的第二场效应晶体管。 第二场效应晶体管包括第二晶体管栅极组件，其包括导电掺杂半导体材料的第二层和至少两层导电氮化物。 本发明还包括场效应晶体管组件，其包括沟道区和沿着沟道区的绝缘材料。 晶体管组件还包括靠近沟道区的栅极堆叠。 栅极堆叠包括通过绝缘材料与沟道区分离的第一导电氮化物层。 堆叠还包括靠近第一导电氮化物层的导电掺杂半导体材料，以及通过导电掺杂的半导体材料与第一导电氮化物层分离的第二导电氮化物层。 此外，本发明包括形成场效应晶体管的方法以及形成集成电路的方法。

    Device having conductive material disposed in a cavity formed in an isolation oxide disposed in a trench
    8.
    发明授权
    Device having conductive material disposed in a cavity formed in an isolation oxide disposed in a trench 有权
    具有设置在形成在设置在沟槽中的隔离氧化物中的空腔中的导电材料的装置

    公开(公告)号：US07804139B2

    公开(公告)日：2010-09-28

    申请号：US11438771

    申请日：2006-05-23

    申请人： Fernando Gonzalez ,  Chandra Mouli

    发明人： Fernando Gonzalez ,  Chandra Mouli

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66636 ,  H01L21/2257 ,  H01L21/823481 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/7834

    摘要： Devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an isolation oxide. Cavities are formed in the isolation oxide and filled with a conductive material, such a doped polysilicon. Doped regions may be formed in the substrate directly adjacent the conductive material to form vertical junctions between the polysilicon and the exposed substrate at the trench sidewalls.

    摘要翻译： 诸如晶体管的器件具有垂直的接合边缘。 更具体地说，浅沟槽形成在衬底中并填充有隔离氧化物。 在隔离氧化物中形成空穴，并填充有导电材料，例如掺杂的多晶硅。 掺杂区域可以形成在直接邻近导电材料的衬底中，以在沟槽侧壁处形成多晶硅和暴露衬底之间的垂直结。

    Transistor surround gate structure with silicon-on-insulator isolation for memory cells, memory arrays, memory devices and systems and methods of forming same
    10.
    发明申请
    Transistor surround gate structure with silicon-on-insulator isolation for memory cells, memory arrays, memory devices and systems and methods of forming same 有权
    用于存储器单元，存储器阵列，存储器件和系统的绝缘体上隔离硅晶体管环绕栅极结构及其形成方法

    公开(公告)号：US20080079053A1

    公开(公告)日：2008-04-03

    申请号：US11541186

    申请日：2006-09-29

    申请人： Fernando Gonzalez ,  Chandra Mouli

    发明人： Fernando Gonzalez ,  Chandra Mouli

    IPC分类号： H01L29/76

    CPC分类号： H01L29/78696 ,  H01L21/28273 ,  H01L21/84 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/42336 ,  H01L29/42392 ,  H01L29/66787 ,  H01L29/66825 ,  H01L29/7881

    摘要： A transistor surround gate structure and a method of forming thereof on a semiconductor assembly are described. The transistor surround gate structure is formed on a partial silicon-on-insulator in one direction and on a full silicon-on insulator in a second direction and may be scaled to 4f2 line width for a memory array. A plurality of transistor surround gate structures are utilized as memory storage cells in various memory device applications, such as a dynamic random access memory application, a flash memory application and a single transistor memory cell is utilized in an embedded memory device application, which provide for the use of any one of the memory device applications to be used in a system.

    摘要翻译： 描述了晶体管环绕栅极结构及其在半导体组件上的形成方法。 晶体管环绕栅极结构在一个方向上的绝缘体上的绝缘体上形成，并且在第二方向上在全硅绝缘体上形成，并且可以缩放到存储器阵列的4f 2线宽 。 多个晶体管环境栅极结构被用作各种存储器件应用中的存储器存储单元，诸如动态随机存取存储器应用，闪速存储器应用和单个晶体管存储单元被用于嵌入式存储器件应用中，其提供 在系统中使用任何一种存储器件应用程序。