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1.发明授权Method and circuit configuration of the parallel input of data into a semiconductor memory 失效将数据并行输入到半导体存储器中的方法和电路配置
公开(公告)号：US4885748A
公开(公告)日：1989-12-05
申请号：US168668
申请日：1988-03-16
申请人： Kurt Hoffmann , Hans-Dieter Oberle , Rainer Kraus , Oskar Kowarik , Manfred Paul
发明人： Kurt Hoffmann , Hans-Dieter Oberle , Rainer Kraus , Oskar Kowarik , Manfred Paul
IPC分类号： G11C29/00 , G11C11/401 , G11C29/34
CPC分类号： G11C29/34
摘要： A method and circuit configuration for the parallel input of data items in the form of a test pattern into a block of a semiconductor memory having a plurality of storage cells. For test purposes, data items are simultaneously input in parallel into the storage cells.
摘要翻译： 一种用于将测试图形形式的数据项并行输入到具有多个存储单元的半导体存储器的块中的方法和电路配置。 为了测试目的，数据项同时并入输入到存储单元中。
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公开(公告)号：US4956819A
公开(公告)日：1990-09-11
申请号：US168653
申请日：1988-03-16
申请人： Kurt Hoffmann , Hans-Dieter Oberle , Rainer Kraus , Oskar Kowarik
发明人： Kurt Hoffmann , Hans-Dieter Oberle , Rainer Kraus , Oskar Kowarik
IPC分类号： G11C29/00 , G11C29/34 , G11C29/36 , G11C29/38 , H03K19/096 , H03K19/173
CPC分类号： H03K19/1736 , G11C29/34 , G11C29/36 , G11C29/38 , H03K19/096 , H03K19/0963
摘要： A circuit configuration and method for testing storage cells of an integrated semiconductor memory precharges a pair of external bit lines to mutually complementary logic levels. All of the storage cells of a word line are always read-out in parallel. In a "no fault" situation the pair of external bit lines retains its precharge level, whereas in the case of a fault, the level of the external bit line which is precharged to logical 1 falls. This is recognized by a discriminator circuit and analyzed.
摘要翻译： 用于测试集成半导体存储器的存储单元的电路配置和方法将一对外部位线预充电到互补的逻辑电平。 字线的所有存储单元总是并行读出。 在“无故障”情况下，一对外部位线保持其预充电电平，而在故障的情况下，预充电到逻辑1的外部位线的电平下降。 这被鉴别器电路识别并分析。
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公开(公告)号：US4922134A
公开(公告)日：1990-05-01
申请号：US309386
申请日：1989-02-10
CPC分类号： G11C29/785
摘要： A redundancy decoder of an integrated semiconductor memory having a plurality of decoder stages containing a switching transistor and a separable connection having respective conditions in which the separable connection is severed and intact, as well as at least one charging transistor, comprising, in each of the decoder stages, an addressing circuit connected to and between the switching transistor and the separable connection of the respective decoder stages, the addressing circuit being electrically simulatable when the respective separable connection is in the intact condition thereof.
摘要翻译： 一种集成半导体存储器的冗余解码器，其具有包含开关晶体管的多个解码器级和具有可分离连接断开和完整的各自条件的可分离连接，以及至少一个充电晶体管，包括： 解码器级，连接到开关晶体管和各个解码器级的可分离连接之间的寻址电路，当相应的可分离连接处于其完整状态时，寻址电路可电可模拟。
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4.发明申请公开(公告)号：US20060273820A1
公开(公告)日：2006-12-07
申请号：US11439450
申请日：2006-05-24
IPC分类号： H03K19/00
CPC分类号： G01R31/318566 , G01R31/318572
摘要： An integrated circuit includes at least one input and output circuit including: a signal terminal that provides an external contact; a protective circuit coupled to the signal terminal; an input driver and/or an output driver coupled to the signal terminal via the protective circuit; and an additional circuit including a first input coupled to the signal terminal via the protective circuit, and an output that provides a test value for operation of the input and output circuit.
摘要翻译： 集成电路包括至少一个输入和输出电路，包括：提供外部触点的信号端; 耦合到信号端子的保护电路; 经由保护电路耦合到信号端子的输入驱动器和/或输出驱动器; 以及附加电路，其包括经由保护电路耦合到信号端子的第一输入端，以及提供用于输入和输出电路的操作的测试值的输出。
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5.发明申请Method and device for detecting period length fluctuations of periodic signals 有权用于检测周期信号周期长度波动的方法和装置公开(公告)号：US20050241362A1
公开(公告)日：2005-11-03
申请号：US10525163
申请日：2003-08-08
IPC分类号： G01R23/10 , G01R29/027 , H04L25/02 , G01R29/02
CPC分类号： H04L25/0262 , G01R23/10 , G01R29/0273
摘要： To determine the period length of a first signal, the length is measured by counting the periods of a second signal with a shorter period length. To measure the fluctuations of the period length of the first signal whilst also taking into account the fluctuations of the period length of the second signal, the measurement is carried out for two different values of the period length of the second signal. Both the fluctuations of the period length of the first signal and the accumulated fluctuations of the period length of the second signal are calculated independently of one another from the two values. The method enables the period length fluctuations of a first signal that originates from a phase-locked loop to be detected.
摘要翻译： 为了确定第一信号的周期长度，通过对具有较短周期长度的第二信号的周期进行计数来测量长度。 为了测量第一信号的周期长度的波动，同时考虑到第二信号的周期长度的波动，对于第二信号的周期长度的两个不同的值进行测量。 从两个值彼此独立地计算第一信号的周期长度的波动和第二信号的周期长度的累积波动。 该方法使得能够检测来自锁相环的第一信号的周期长度波动。
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6.发明授权公开(公告)号：US06944810B2
公开(公告)日：2005-09-13
申请号：US10213728
申请日：2002-08-06
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/319 , G01R31/28
CPC分类号： G01R31/31715 , G01R31/318572 , G01R31/31905
摘要： In order to test the input and output drivers of a circuit, in particular an integrated semiconductor circuit, a method and apparatus is provided to connect the input or output drivers assigned to individual signal connections of the circuit to be tested in series to a ring oscillator or to an open chain with the oscillation of the ring oscillator or the delay time being evaluated. By providing appropriate controllable switches, the configuration of the ring oscillator or the chain can be altered variably depending on the input or output drivers to be tested respectively. In this way an “at-speed” and “leakage” test of all input and output drivers, including the external signal connections, are possible with all of these having to be connected to a rapid test unit.
摘要翻译： 为了测试电路的输入和输出驱动器，特别是集成半导体电路，提供了一种方法和装置，用于将分配给待测试电路的各个信号连接的输入或输出驱动器串联连接到环形振荡器 或者与环形振荡器的振荡或延迟时间进行评估的开链。 通过提供适当的可控开关，环形振荡器或链条的配置可以根据要分别测试的输入或输出驱动器而变化。 以这种方式，所有输入和输出驱动器（包括外部信号连接）的“速度”和“泄漏”测试都是可能的，其中所有这些都必须连接到快速测试单元。
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7.发明授权Apparatus and method for tolerance analysis for digital and/or digitized measure values 有权用于数字和/或数字化测量值的容差分析的装置和方法公开(公告)号：US07487060B2
公开(公告)日：2009-02-03
申请号：US10546073
申请日：2004-02-04
IPC分类号： G06F19/00
CPC分类号： G01R31/31707 , G01R31/31703 , G01R31/3187 , G06F7/026
摘要： An electric tolerance analysis circuit for digital and digitized measured values has inputs for receiving a measured value, a reference value, and a tolerance value and also an output for transmitting an output value. The electric tolerance analysis circuit also has a checking device for checking the measured value using at least one prescribable tolerance criterion and has an output device for outputting an output value which is obtained from the state of the checking device, depending on whether or not the measured value meets the respective prescribed tolerance criterion.
摘要翻译： 用于数字和数字化测量值的电容差分析电路具有用于接收测量值，参考值和公差值的输入端，以及用于传输输出值的输出。 电容差分析电路还具有用于使用至少一个可规定的公差标准来检查测量值的检查装置，并且具有输出装置，用于输出从检查装置的状态获得的输出值，这取决于所测量的 值符合相应规定的公差标准。
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8.发明授权Input and output circuit of an integrated circuit and a method for testing the same 有权集成电路的输入和输出电路及其测试方法公开(公告)号：US07453282B2
公开(公告)日：2008-11-18
申请号：US11439450
申请日：2006-05-24
IPC分类号： H03K19/00
CPC分类号： G01R31/318566 , G01R31/318572
摘要： An integrated circuit includes at least one input and output circuit including: a signal terminal that provides an external contact; a protective circuit coupled to the signal terminal; an input driver and/or an output driver coupled to the signal terminal via the protective circuit; and an additional circuit including a first input coupled to the signal terminal via the protective circuit, and an output that provides a test value for operation of the input and output circuit.
摘要翻译： 集成电路包括至少一个输入和输出电路，包括：提供外部触点的信号端; 耦合到信号端子的保护电路; 经由保护电路耦合到信号端子的输入驱动器和/或输出驱动器; 以及附加电路，其包括经由保护电路耦合到信号端子的第一输入端，以及提供用于输入和输出电路的操作的测试值的输出。
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9.发明申请Apparatus and Method for Tolerance Analysis for Digital and/or Digitized Measure Values 有权用于数字和/或数字化测量值的容差分析的装置和方法公开(公告)号：US20070239385A1
公开(公告)日：2007-10-11
申请号：US10546073
申请日：2004-02-04
IPC分类号： G06F19/00
CPC分类号： G01R31/31707 , G01R31/31703 , G01R31/3187 , G06F7/026
摘要： An electric tolerance analysis circuit for digital and digitized measured values has inputs for receiving a measured value, a reference value, and a tolerance value and also an output for transmitting an output value. The electric tolerance analysis circuit also has a checking device for checking the measured value using at least one prescribable tolerance criterion and has an output device for outputting an output value which is obtained from the state of the checking device, depending on whether or not the measured value meets the respective prescribed tolerance criterion.
摘要翻译： 用于数字和数字化测量值的电容差分析电路具有用于接收测量值，参考值和公差值的输入端，以及用于传输输出值的输出。 电容差分析电路还具有用于使用至少一个可规定的公差标准来检查测量值的检查装置，并且具有输出装置，用于输出从检查装置的状态获得的输出值，这取决于所测量的 值符合相应规定的公差标准。
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10.发明授权Method and device for detecting period length fluctuations of periodic signals 有权用于检测周期信号周期长度波动的方法和装置公开(公告)号：US07254502B2
公开(公告)日：2007-08-07
申请号：US10525163
申请日：2003-08-08
IPC分类号： G01R29/02
CPC分类号： H04L25/0262 , G01R23/10 , G01R29/0273
摘要： To determine the period length of a first signal, the length is measured by counting the periods of a second signal with a shorter period length. To measure the fluctuations of the period length of the first signal whilst also taking into account the fluctuations of the period length of the second signal, the measurement is carried out for two different values of the period length of the second signal. Both the fluctuations of the period length of the first signal and the accumulated fluctuations of the period length of the second signal are calculated independently of one another from the two values. The method enables the period length fluctuations of a first signal that originates from a phase-locked loop to be detected.
摘要翻译： 为了确定第一信号的周期长度，通过对具有较短周期长度的第二信号的周期进行计数来测量长度。 为了测量第一信号的周期长度的波动，同时考虑到第二信号的周期长度的波动，对于第二信号的周期长度的两个不同的值进行测量。 从两个值彼此独立地计算第一信号的周期长度的波动和第二信号的周期长度的累积波动。 该方法使得能够检测来自锁相环的第一信号的周期长度波动。
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