Organic Semiconductor Interface Preparation
    1.
    发明申请
    Organic Semiconductor Interface Preparation 有权
    有机半导体界面准备

    公开(公告)号:US20120146002A1

    公开(公告)日:2012-06-14

    申请号:US12968102

    申请日:2010-12-14

    摘要: A method is provided for preparing an interface surface for the deposition of an organic semiconductor material, in the fabrication of an organic thin film transistor (OTFT). A substrate is provided and a gate electrode is formed overlying the substrate. A gate dielectric is formed overlying the gate electrode. Then, source (S) and drain (D) electrodes are formed overlying the gate dielectric, exposing a gate dielectric channel interface region between the S/D electrodes. Subsequent to exposing the OTFT to a H2 or N2 plasma, a self-assembled organic monolayer is formed overlying the S/D electrodes. Finally, an active organic semiconductor layer is formed over the S/D electrodes and gate dielectric channel interface. The OTFT may be exposed to plasma either before or after the formation of the S/D electrodes.

    摘要翻译: 在有机薄膜晶体管(OTFT)的制造中提供了一种制备用于沉积有机半导体材料的界面的方法。 提供衬底并且形成覆盖衬底的栅电极。 在栅电极上形成栅极电介质。 然后,源极(S)和漏极(D)电极形成在栅极电介质上方,暴露在S / D电极之间的栅介质沟道界面区域。 在将OTFT暴露于H 2或N 2等离子体之后,形成覆盖S / D电极的自组装有机单层。 最后,在S / D电极和栅介质通道界面上形成有源有机半导体层。 在形成S / D电极之前或之后,OTFT可能暴露于等离子体。

    Electrohydrodynamic (EHD) Printing for the Defect Repair of Contact Printed Circuits
    2.
    发明申请
    Electrohydrodynamic (EHD) Printing for the Defect Repair of Contact Printed Circuits 有权
    电动液压(EHD)打印用于接触印刷电路的缺陷修复

    公开(公告)号:US20140158399A1

    公开(公告)日:2014-06-12

    申请号:US13711192

    申请日:2012-12-11

    IPC分类号: H05K3/00 H05K1/02

    摘要: A method is provided for repairing defects in a contact printed circuit. The method provides a substrate with a contact printed circuit formed on a substrate top surface. After detecting a discontinuity in a printed circuit feature, a bias voltage is applying to at least one of a first region of the printed circuit feature or a second region of the printed circuit feature. The bias voltage may also be applied to both the first and second regions. An electric field is formed between the bias voltage and an ink delivery nozzle having a voltage potential less than the bias voltage. Conductive ink is attracted into the electric field from the ink delivery nozzle. Conductive is printed ink on the discontinuity, forming a conductive printed bridge. Typically, the ink delivery nozzle is an electrohydrodynamic (EHD) printing nozzle.

    摘要翻译: 提供一种用于修复接触式印刷电路中的缺陷的方法。 该方法提供了在基板顶表面上形成有接触印刷电路的基板。 在检测到印刷电路特征中的不连续性之后,偏压被施加到印刷电路特征的第一区域或印刷电路特征的第二区域中的至少一个。 偏置电压也可以施加到第一和第二区域。 在偏置电压和具有小于偏置电压的电压电位的墨水输出喷嘴之间形成电场。 导电油墨从油墨输送喷嘴吸入电场。 导电印刷油墨在不连续处,形成导电印刷桥。 通常,墨水输送喷嘴是电动液压(EHD)印刷喷嘴。

    Organic transistor with fluropolymer banked crystallization well
    3.
    发明授权
    Organic transistor with fluropolymer banked crystallization well 有权
    有机晶体管与氟聚合物结合良好

    公开(公告)号:US08399290B2

    公开(公告)日:2013-03-19

    申请号:US13009806

    申请日:2011-01-19

    IPC分类号: H01L21/40

    摘要: A method is provided for fabricating a printed organic thin film transistor (OTFT) with a patterned organic semiconductor using a fluropolymer banked crystallization well. In the case of a bottom gate OTFT, a substrate is provided and a gate electrode is formed overlying the substrate. A gate dielectric is formed overlying the gate electrode, and source (S) and drain (D) electrodes are formed overlying the gate dielectric. A gate dielectric OTFT channel interface region is formed between the S/D electrodes. A well with fluropolymer containment and crystallization banks is then formed, to define an organic semiconductor print area. The well is filled with an organic semiconductor, covering the S/D electrodes and the gate dielectric OTFT channel interface. Then, the organic semiconductor is crystallized. Predominant crystal grain nucleation originates from regions overlying the S/D electrodes. As a result, an organic semiconductor channel is formed, interposed between the S/D electrodes.

    摘要翻译: 提供了一种使用氟聚合物分层结晶井制造具有图案化有机半导体的印刷有机薄膜晶体管(OTFT)的方法。 在底栅OTFT的情况下,提供衬底并且形成覆盖衬底的栅电极。 形成覆盖栅电极的栅极电介质,并且覆盖栅极电介质形成源极(S)和漏极(D)电极。 在S / D电极之间形成栅极介电OTFT沟道界面区域。 然后形成具有氟聚合物封存和结晶团的阱,以限定有机半导体印刷区域。 该阱填充有机半导体,覆盖S / D电极和栅极介电OTFT通道界面。 然后,有机半导体结晶。 主要晶粒成核起源于覆盖S / D电极的区域。 结果,形成介于S / D电极之间的有机半导体沟道。

    Controlling printed ink line widths using fluoropolymer templates
    4.
    发明授权
    Controlling printed ink line widths using fluoropolymer templates 有权
    使用氟聚合物模板控制印刷墨水线宽度

    公开(公告)号:US08765224B2

    公开(公告)日:2014-07-01

    申请号:US13432855

    申请日:2012-03-28

    IPC分类号: B05D5/00

    摘要: A method is provided for controlling printed ink horizontal cross-sectional areas using fluoropolymer templates. The method initially forms a fluoropolymer template overlying a substrate. The fluoropolymer template has a horizontal first cross-sectional dimension. Then, a primary ink is printed overlying the fluoropolymer template having a horizontal second cross-sectional dimension less than the first cross-sectional dimension. In the case of a fluoropolymer line having a template length greater than a template width, where the template width is the first cross-sectional dimension, printing the primary ink entails printing a primary ink line having an ink length greater than an ink width, where the ink width is the second cross-sectional dimension. In one aspect, the method prints a plurality of primary ink layers, each primary ink layer having an ink width less than the template width. Each overlying primary ink layer can be printed prior to solvents in underlying primary ink layers evaporating.

    摘要翻译: 提供了一种使用氟聚合物模板控制印刷油墨水平横截面积的方法。 该方法最初形成覆盖在基底上的氟聚合物模板。 氟聚合物模板具有水平的第一横截面尺寸。 然后,将初级墨水印刷在具有小于第一横截面尺寸的水平第二横截面尺寸的含氟聚合物模板上。 在具有模板长度大于模板宽度的含氟聚合物线的情况下,其中模板宽度是第一横截面尺寸,打印初级墨水需要打印墨水长度大于墨水宽度的主墨水线,其中 油墨宽度是第二横截面尺寸。 在一个方面,该方法印刷多个主油墨层,每个主油墨层的油墨宽度小于模板宽度。 每个上覆的初级墨水层可以在溶剂之前被打印在基本的主油墨层中蒸发。

    Organic Transistor with Fluropolymer Banked Crystallization Well
    5.
    发明申请
    Organic Transistor with Fluropolymer Banked Crystallization Well 有权
    有机晶体管与氟聚合物堆积结晶井

    公开(公告)号:US20120181512A1

    公开(公告)日:2012-07-19

    申请号:US13009806

    申请日:2011-01-19

    IPC分类号: H01L51/10 H01L51/40

    摘要: A method is provided for fabricating a printed organic thin film transistor (OTFT) with a patterned organic semiconductor using a fluropolymer banked crystallization well. In the case of a bottom gate OTFT, a substrate is provided and a gate electrode is formed overlying the substrate. A gate dielectric is formed overlying the gate electrode, and source (S) and drain (D) electrodes are formed overlying the gate dielectric. A gate dielectric OTFT channel interface region is formed between the S/D electrodes. A well with fluropolymer containment and crystallization banks is then formed, to define an organic semiconductor print area. The well is filled with an organic semiconductor, covering the S/D electrodes and the gate dielectric OTFT channel interface. Then, the organic semiconductor is crystallized. Predominant crystal grain nucleation originates from regions overlying the S/D electrodes. As a result, an organic semiconductor channel is formed, interposed between the S/D electrodes.

    摘要翻译: 提供了一种使用氟聚合物分层结晶井制造具有图案化有机半导体的印刷有机薄膜晶体管(OTFT)的方法。 在底栅OTFT的情况下,提供衬底并且形成覆盖衬底的栅电极。 形成覆盖栅电极的栅极电介质,并且覆盖栅极电介质形成源极(S)和漏极(D)电极。 在S / D电极之间形成栅极介电OTFT沟道界面区域。 然后形成具有氟聚合物封存和结晶团的阱,以限定有机半导体印刷区域。 该阱填充有机半导体,覆盖S / D电极和栅极介电OTFT通道界面。 然后,有机半导体结晶。 主要晶粒成核起源于覆盖S / D电极的区域。 结果,形成介于S / D电极之间的有机半导体沟道。

    Organic semiconductor interface preparation
    6.
    发明授权
    Organic semiconductor interface preparation 有权
    有机半导体界面制备

    公开(公告)号:US08367459B2

    公开(公告)日:2013-02-05

    申请号:US12968102

    申请日:2010-12-14

    IPC分类号: H01L51/00

    摘要: A method is provided for preparing an interface surface for the deposition of an organic semiconductor material, in the fabrication of an organic thin film transistor (OTFT). A substrate is provided and a gate electrode is formed overlying the substrate. A gate dielectric is formed overlying the gate electrode. Then, source (S) and drain (D) electrodes are formed overlying the gate dielectric, exposing a gate dielectric channel interface region between the S/D electrodes. Subsequent to exposing the OTFT to a H2 or N2 plasma, a self-assembled organic monolayer is formed overlying the S/D electrodes. Finally, an active organic semiconductor layer is formed over the S/D electrodes and gate dielectric channel interface. The OTFT may be exposed to plasma either before or after the formation of the S/D electrodes.

    摘要翻译: 在有机薄膜晶体管(OTFT)的制造中提供了一种制备用于沉积有机半导体材料的界面的方法。 提供衬底并且形成覆盖衬底的栅电极。 在栅电极上形成栅极电介质。 然后,源极(S)和漏极(D)电极形成在栅极电介质上方,暴露在S / D电极之间的栅介质沟道界面区域。 在将OTFT暴露于H 2或N 2等离子体之后,形成覆盖S / D电极的自组装有机单层。 最后,在S / D电极和栅介质通道界面上形成有源有机半导体层。 在形成S / D电极之前或之后,OTFT可能暴露于等离子体。

    Selective growth of ZnO nanostructure using a patterned ALD ZnO seed layer
    7.
    发明授权
    Selective growth of ZnO nanostructure using a patterned ALD ZnO seed layer 失效
    使用图案化的ALD ZnO种子层选择性生长ZnO纳米结构

    公开(公告)号:US07303631B2

    公开(公告)日:2007-12-04

    申请号:US10977430

    申请日:2004-10-29

    IPC分类号: C30B25/04

    摘要: Patterned zinc-oxide nanostructures are grown without using a metal catalyst by forming a seed layer of polycrystalline zinc oxide on a surface of a substrate. The seed layer can be formed by an atomic layer deposition technique. The seed layer is patterned, such as by etching, and growth of at least one zinc-oxide nanostructure is induced substantially over the patterned seed layer by, for example, exposing the patterned seed layer to zinc vapor in the presence of a trace amount of oxygen. The seed layer can alternatively be formed by using a spin-on technique, such as a metal organic deposition technique, a spray pyrolisis technique, an RF sputtering technique or by oxidation of a zinc thin film layer formed on the substrate.

    摘要翻译: 通过在基板的表面上形成多晶氧化锌的晶种层,生长图案化的氧化锌纳米结构而不使用金属催化剂。 种子层可以通过原子层沉积技术形成。 种子层被图案化,例如通过蚀刻,并且基本上在图案化种子层上诱导至少一种氧化锌纳米结构的生长,例如通过例如将图案化的种子层在痕量的 氧。 种子层可以替代地通过使用旋涂技术形成,例如金属有机沉积技术,喷雾热解技术,RF溅射技术或通过氧化形成在基底上的锌薄膜层。

    Method to fabricate a nanowire CHEMFET sensor device using selective nanowire deposition
    8.
    发明授权
    Method to fabricate a nanowire CHEMFET sensor device using selective nanowire deposition 失效
    使用选择性纳米线沉积制造纳米线CHEMFET传感器器件的方法

    公开(公告)号:US07309621B2

    公开(公告)日:2007-12-18

    申请号:US11115814

    申请日:2005-04-26

    摘要: A method of fabricating a nanowire CHEMFET sensor mechanism includes preparing a silicon substrate; depositing a polycrystalline ZnO seed layer on the silicon substrate; patterning and etching the polycrystalline ZnO seed layer; depositing an insulating layer over the polycrystalline ZnO seed layer and the silicon substrate; patterning and etching the insulating layer to form contact holes to a source region and a drain region; metallizing the contact holes to form contacts for the source region and the drain region; depositing a passivation dielectric layer over the insulating layer and the contacts; patterning the passivation layer and etching to expose the polycrystalline ZnO seed layer between the source region and the drain region; and growing ZnO nanostructures on the exposed ZnO seed layer to form a ZnO nanostructure CHEMFET sensor device.

    摘要翻译: 制造纳米线CHEMFET传感器机构的方法包括制备硅衬底; 在硅衬底上沉积多晶ZnO种子层; 图案化和蚀刻多晶ZnO种子层; 在多晶ZnO种子层和硅衬底上沉积绝缘层; 图案化和蚀刻绝缘层以形成到源极区域和漏极区域的接触孔; 金属化接触孔以形成用于源极区域和漏极区域的触点; 在所述绝缘层和所述触点上沉积钝化介电层; 图案化钝化层并蚀刻以在源极区域和漏极区域之间暴露多晶ZnO晶种层; 并在曝光的ZnO种子层上生长ZnO纳米结构以形成ZnO纳米结构CHEMFET传感器装置。

    One mask Pt/PCMO/Pt stack etching process for RRAM applications
    10.
    发明授权
    One mask Pt/PCMO/Pt stack etching process for RRAM applications 有权
    用于RRAM应用的一个掩模Pt / PCMO / Pt堆叠蚀刻工艺

    公开(公告)号:US07169637B2

    公开(公告)日:2007-01-30

    申请号:US10883228

    申请日:2004-07-01

    IPC分类号: H01L21/06 H01L21/461

    摘要: A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.

    摘要翻译: 包含含PCMO的RRAM以减少堆叠侧壁残留物的单掩模蚀刻方法包括制备从由硅,二氧化硅和多晶硅组成的一组衬底取得的衬底; 在底物上沉积底部电极; 在底部电极上沉​​积PCMO层; 在PCMO层上沉积顶部电极; 在顶部电极上沉​​积硬掩模; 在硬掩模上沉积和图案化光致抗蚀剂层; 蚀刻硬掩模; 使用具有由Ar,O 2和Cl 2组成的蚀刻气氛的第一蚀刻工艺蚀刻顶部电极; 使用从由第一蚀刻工艺和由Ar和O 2组成的蚀刻气氛的第二蚀刻工艺组成的蚀刻工艺组中的蚀刻工艺来蚀刻PCMO层。 使用第一蚀刻工艺蚀刻底部电极; 并完成RRAM设备。