公开(公告)号：US20080132014A1

公开(公告)日：2008-06-05

申请号：US12012593

申请日：2008-02-04

Applicant: Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

Inventor： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

IPC: H01L21/336

CPC classification number: H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

Abstract translation: 提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的基板上。 具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。 在第一区域中，分开形成第一漏极区域和第二浮动区域。 在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。 第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。 第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。 也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度 杂质区。

公开(公告)号：US20060006453A1

公开(公告)日：2006-01-12

申请号：US11099658

申请日：2005-04-06

Applicant: Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

Inventor： Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

Abstract translation: 在非易失性半导体存储器件及其制造方法中，非易失性半导体存储器件包括半导体衬底中的单元掺杂区域和源极/漏极区域，该单元掺杂区域被掺杂为第一导电类型，沟道区域 设置在半导体衬底中的源极/漏极区之间，形成在电池掺杂区的上部的预定区域中的第一导电类型的隧道掺杂区，掺杂浓度高于 在隧道掺杂区域上形成在半导体衬底的表面上的隧道绝缘层，围绕隧道绝缘层并覆盖沟道区域的栅极绝缘层和暴露在隧道掺杂区域外的电池掺杂区域，以及 栅电极覆盖隧道绝缘层和栅极绝缘层。

公开(公告)号：US20080293200A1

公开(公告)日：2008-11-27

申请号：US12219995

申请日：2008-07-31

Applicant: Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

Inventor： Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

Abstract translation: 在非易失性半导体存储器件及其制造方法中，非易失性半导体存储器件包括半导体衬底中的单元掺杂区域和源极/漏极区域，该单元掺杂区域被掺杂为第一导电类型，沟道区域 设置在半导体衬底中的源极/漏极区之间，形成在电池掺杂区的上部的预定区域中的第一导电类型的隧道掺杂区，掺杂浓度高于 在隧道掺杂区域上形成在半导体衬底的表面上的隧道绝缘层，围绕隧道绝缘层并覆盖沟道区域的栅极绝缘层和暴露在隧道掺杂区域外的电池掺杂区域，以及 栅电极覆盖隧道绝缘层和栅极绝缘层。

公开(公告)号：US20080112840A1

公开(公告)日：2008-05-15

申请号：US11722341

申请日：2005-12-22

Applicant: Kwang-tae Kim ,  Yong-Heon Lee ,  Won-qeun Son

Inventor： Kwang-tae Kim ,  Yong-Heon Lee ,  Won-qeun Son

IPC: C22C38/44 ,  C22C38/58

CPC classification number: C22C38/44 ,  C22C38/001 ,  C22C38/58

Abstract: Disclosed is duplex stainless steel that containes relatively low content of Ni, and limits constituents of Cr—Mo—Mn—N to make volume fraction of α and γ have about 50:50, thereby minimizing incidence of a edge crack to enhance a production yield and decrease a processing load, in which the alloy constituents includes Cr of 19.5˜22.5%. Mo of 0.5-2.5%, Ni if 1.0-3.0%, Mn of 1.5-4.5%, N of 0.15-0.25%, Fe and unavoidable elements, and a constitution range of the alloy constituents are adjusted to make a CPt higher than 20° C. depending on the constitution range of the alloy constituents. Thus, the contents of Cr, Mo and Ni is decreased and the content of Mn is increased a little, so that a production cost thereof is reduced; the corrosion resistance is secured to be better than the STS 304 steel and the 316L steel; the incidence of the edge cract is decreased while being hot-rolled, thereby decreasing a load on the following process; and the surface defective is decreased, thereby improving a production yield.

Abstract translation: 公开了含有相对低含量的Ni的双相不锈钢，并且限制Cr-Mo-Mn-N的组分使得α和γ的体积分数具有约50:50，从而使边缘裂纹的发生率最小化以提高生产率 并减少加工负荷，其中合金成分含有19.5〜22.5％的Cr。 Mo为0.5-2.5％，Ni为1.0-3.0％，Mn为1.5-4.5％，N为0.15-0.25％，Fe和不可避免的元素，以及合金成分的组成范围，使得CPt高于20 取决于合金成分的构成范围。 因此，Cr，Mo，Ni的含量降低，Mn含量增加一点，生产成本降低; 确保耐腐蚀性优于STS 304钢和316L钢; 在热轧时，边缘的发生率降低，从而在以下过程中减少负载; 表面缺陷减少，提高了生产率。

公开(公告)号：US07408219B2

公开(公告)日：2008-08-05

申请号：US11099658

申请日：2005-04-06

Applicant: Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

Inventor： Tea-kwang Yu ,  Weon-ho Park ,  Kyoung-hwan Kim ,  Kwang-tae Kim

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.

Abstract translation: 在非易失性半导体存储器件及其制造方法中，非易失性半导体存储器件包括半导体衬底中的单元掺杂区域和源极/漏极区域，该单元掺杂区域被掺杂为第一导电类型，沟道区域 设置在半导体衬底中的源极/漏极区之间，形成在电池掺杂区的上部的预定区域中的第一导电类型的隧道掺杂区，掺杂浓度高于 在隧道掺杂区域上形成在半导体衬底的表面上的隧道绝缘层，围绕隧道绝缘层并覆盖沟道区域的栅极绝缘层和暴露在隧道掺杂区域外的电池掺杂区域，以及 栅电极覆盖隧道绝缘层和栅极绝缘层。

公开(公告)号：US20070262373A1

公开(公告)日：2007-11-15

申请号：US11800650

申请日：2007-05-07

Applicant: Weon-ho Park ,  Jeong-uk Han ,  Yong-tae Kim ,  Tea-kwang Yu ,  Kwang-tae Kim ,  Ji-hoon Park

Inventor： Weon-ho Park ,  Jeong-uk Han ,  Yong-tae Kim ,  Tea-kwang Yu ,  Kwang-tae Kim ,  Ji-hoon Park

IPC: H01L29/792

CPC classification number: H01L29/7885 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324

Abstract: A non-volatile memory integrated circuit device and a method of fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, a tunneling dielectric layer, a memory gate and a select gate, a floating junction region, a bit line junction region and a common source region, and a tunneling-prevention dielectric layer pattern. The tunneling dielectric layer is formed on the semiconductor substrate. The memory gate and a select gate are formed on the tunneling dielectric layer to be spaced apart from each other. The floating junction region is formed within the semiconductor substrate between the memory gate and the select gate, the bit line junction region is formed opposite the floating junction region with respect to the memory gate, and a common source region is formed opposite the floating junction region with respect to the select gate. The tunneling-prevention dielectric layer pattern is interposed between the semiconductor substrate and the tunneling dielectric layer, and is configured to overlap part of the memory gate.

Abstract translation: 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，隧道电介质层，存储栅极和选择栅极，浮置结区域，位线结区域和公共源极区域，以及防止隧道的电介质层图案 。 隧道介电层形成在半导体衬底上。 存储器栅极和选择栅极形成在隧道电介质层上以彼此间隔开。 在存储栅极和选择栅极之间的半导体衬底内形成浮点结区域，与存储栅极相对地形成位线接合区域，并且与浮置结区域相对形成公共源极区域 相对于选择门。 防止隧道的电介质层图案介于半导体衬底和隧穿电介质层之间，并被配置为与存储器栅极的一部分重叠。

公开(公告)号：US20050117443A1

公开(公告)日：2005-06-02

申请号：US10997835

申请日：2004-11-24

Applicant: Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

Inventor： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

IPC: H01L27/115 ,  G11C8/02 ,  H01L21/8247

CPC classification number: H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

Abstract translation: 提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的衬底上。 具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。 在第一区域中，第一漏极区域和第二浮动区域彼此分开地形成。 在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。 第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。 第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。 也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度 杂质区。

公开(公告)号：US08922529B2

公开(公告)日：2014-12-30

申请号：US13398903

申请日：2012-02-17

Applicant: Kwang-tae Kim

Inventor： Kwang-tae Kim

IPC: G06F3/043 ,  G09G5/00 ,  G06F3/041

CPC classification number: G06F3/0433 ,  G06F3/043

Abstract: A touch sensor system using vibration at touch point is provided, which includes a first sensor bar having a piezoelectric grid formed on a side surface thereof, a second sensor unit having a piezoelectric grid formed on a side surface thereof, and connected at one end to an end of the first sensor bar in a perpendicular relation, a signal processing unit connected to the first and second sensor units to receive an electric signal, and a touch point calculating unit which calculates a location of touch with respect to a screen through which the touch is inputted, based on the electric signal received at the signal processing unit.

Abstract translation: 提供了一种在接触点处使用振动的触摸传感器系统，其包括在其侧表面上形成有压电栅格的第一传感器棒，具有形成在其侧表面上的压电栅格的第二传感器单元，并且一端连接到 垂直关系的第一传感器杆的端部，连接到第一和第二传感器单元以接收电信号的信号处理单元，以及触摸点计算单元，其计算相对于屏幕的触摸位置， 基于在信号处理单元处接收的电信号输入触摸。

公开(公告)号：US07352026B2

公开(公告)日：2008-04-01

申请号：US10997835

申请日：2004-11-24

Applicant: Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

Inventor： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

IPC: H01L29/788 ,  H01L29/76

CPC classification number: H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

公开(公告)号：US4933465A

公开(公告)日：1990-06-12

申请号：US292536

申请日：1988-12-30

Applicant: Kwang-tae Kim ,  Young-soo Kim ,  Jin-youl Kim

Inventor： Kwang-tae Kim ,  Young-soo Kim ,  Jin-youl Kim

IPC: C07D231/52 ,  G03C7/384

CPC classification number: G03C7/384 ,  C07D231/52

Abstract: A magenta color - forming coupler represented by the formula (1) for use in color photographic silver halide photosensitive material: ##STR1## wherein X is halogen; l is 0, 1, 2, or 3; Y is hydrogen or halogen; Q is --NH-- or --NHCO--; n is 1, 2, or 3; K is O, S, or SO.sub.2 ; A is ##STR2## or ##STR3## in which R.sup.1 represents C.sub.1 -C.sub.8 alkylene or phenylene, R.sup.2 represents C.sub.1`-C.sub.4 alkylene or phenylene and q is 1, 2, or 3; R.sup.3 is C.sub.1 -C.sub.8 alkylene; R.sup.4 is C.sub.1 -C.sub.8 alkyl; and m is an integer of 0, 1, or 2, provided that a plurality of R.sup.4 are the same or different each other when m is 2, and a photographic photosensitive material containing the magenta coupler above.

Abstract translation: 用于彩色照相卤化银感光材料的由式（1）表示的品红色成色剂：其中X是卤素; l为0,1,2或3; Y是氢或卤素; Q是-NH-或-NHCO-; n为1,2或3; K是O，S或SO 2; A为或，其中R1表示C1-C8亚烷基或亚苯基，R2表示C1'-C4亚烷基或亚苯基，q为1,2或3; R3是C1-C8亚烷基; R4是C1-C8烷基; m为0，1或2的整数，条件是当m为2时，多个R 4相同或不同，以及含有品红色成色剂的感光感光材料。