High sensitivity and high dynamic-range CMOS image sensor pixel structure with dynamic C-V characteristics
    1.
    发明申请
    High sensitivity and high dynamic-range CMOS image sensor pixel structure with dynamic C-V characteristics 审中-公开
    高灵敏度和高动态范围CMOS图像传感器像素结构具有动态C-V特性

    公开(公告)号:US20070252073A1

    公开(公告)日:2007-11-01

    申请号:US11653438

    申请日:2007-01-16

    IPC分类号: H04N3/14

    摘要: A new photogate pixel structure for high performance CMOS Image Sensors is proposed. A new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance characteristics, which can be controlled by varying the control-voltage at the photogate node. Since the sensitivity is inversely proportional to the integration capacitance, the dynamic integration capacitance characteristics can provide the new functionality and controllability for high sensitivity and high dynamic range. At a low voltage level of the photogate, the pixel sensitivity of the new photogate pixel structure is maximized due to the minimum value of the integration capacitance. At a high voltage of the photogate, the dynamic range of the new structure can be maximized due to the increased well capacity. In addition, at an optimum bias voltage of the photogate, both the dynamic-range and the sensitivity can be simultaneously improved. Consequently, the new pixel structure allows performance tunability as well as optimization in both the dynamic range and the sensitivity of the image sensor cell.

    摘要翻译: 提出了一种用于高性能CMOS图像传感器的新型光栅像素结构。 新的光栅结构被并入到光电二极管有源像素结构中。 所提出的像素结构表现出动态积分电容特性,其可以通过改变光栅节点处的控制电压来控制。 由于灵敏度与积分电容成反比,动态积分电容特性可为高灵敏度和高动态范围提供新的功能和可控性。 在光栅的低电压电平下,由于积分电容的最小值,新的光栅像素结构的像素灵敏度最大化。 在光栅的高电压下,由于井容量的增加,新结构的动态范围可以最大化。 另外,在光栅的最佳偏置电压下,可以同时提高动态范围和灵敏度。 因此,新的像素结构允许性能可调性以及图像传感器单元的动态范围和灵敏度的优化。

    High Sensitivity and High Dynamic-Range CMOS Image Sensor Pixel Structure with Dynamic C-V Characteristics
    2.
    发明申请
    High Sensitivity and High Dynamic-Range CMOS Image Sensor Pixel Structure with Dynamic C-V Characteristics 审中-公开
    具有动态C-V特性的高灵敏度和高动态范围CMOS图像传感器像素结构

    公开(公告)号:US20080029795A1

    公开(公告)日:2008-02-07

    申请号:US11624592

    申请日:2007-01-18

    IPC分类号: H01L31/062

    摘要: A new photogate pixel structure for high performance CMOS Image Sensors is proposed. A new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance characteristics, which can be controlled by varying the control-voltage at the photogate node. Since the sensitivity is inversely proportional to the integration capacitance, the dynamic integration capacitance characteristics can provide the new functionality and controllability for high sensitivity and high dynamic range. At a low voltage level of the photogate, the pixel sensitivity of the new photogate pixel structure is maximized due to the minimum value of the integration capacitance. At a high voltage of the photogate, the dynamic range of the new structure can be maximized due to the increased well capacity. In addition, at an optimum bias voltage of the photogate, both the dynamic-range and the sensitivity can be simultaneously improved. Consequently, the new pixel structure allows performance tunability as well as optimization in both the dynamic range and the sensitivity of the image sensor cell.

    摘要翻译: 提出了一种用于高性能CMOS图像传感器的新型光栅像素结构。 新的光栅结构被并入到光电二极管有源像素结构中。 所提出的像素结构表现出动态积分电容特性,其可以通过改变光栅节点处的控制电压来控制。 由于灵敏度与积分电容成反比,动态积分电容特性可为高灵敏度和高动态范围提供新的功能和可控性。 在光栅的低电压电平下,由于积分电容的最小值,新的光栅像素结构的像素灵敏度最大化。 在光栅的高电压下,由于井容量的增加,新结构的动态范围可以最大化。 另外,在光栅的最佳偏置电压下,可以同时提高动态范围和灵敏度。 因此,新的像素结构允许性能可调性以及图像传感器单元的动态范围和灵敏度的优化。

    RTD-HBT differential oscillator topology
    3.
    发明授权
    RTD-HBT differential oscillator topology 失效
    RTD-HBT差分振荡器拓扑

    公开(公告)号:US07573343B2

    公开(公告)日:2009-08-11

    申请号:US11463669

    申请日:2006-08-10

    IPC分类号: H03B7/14 H03K3/315

    摘要: The new RTD-HBT differential oscillator circuit topology is proposed. At the nodes of the inductors and varactors in the conventional differential oscillator topology, each the RTD is attached to increase the magnitude of the negative conductance, which results in performance improvement in both the RF output power and phase noise. And, the differential sinusoidal voltage waveform which is essential for the wireless communication system are generated. In addition, the DC power consumption RTD-HBT differential oscillator circuit is similar to the conventional HBT differential oscillator due to the small DC power consumption performance of the RTD.

    摘要翻译: 提出了新的RTD-HBT差分振荡器电路拓扑结构。 在常规差分振荡器拓扑中的电感器和变容二极管的节点处,每个RTD被连接以增加负电导的幅度,这导致RF输出功率和相位噪声两者的性能提高。 并且,产生对于无线通信系统必不可少的差分正弦电压波形。 此外,直流功耗RTD-HBT差分振荡电路由于RTD的小直流功耗特性,与传统的HBT差分振荡器相似。

    DATA RECEIVER AND DATA RECEIVING METHOD
    4.
    发明申请
    DATA RECEIVER AND DATA RECEIVING METHOD 有权
    数据接收器和数据接收方法

    公开(公告)号:US20080174343A1

    公开(公告)日:2008-07-24

    申请号:US11677779

    申请日:2007-02-22

    IPC分类号: H03K5/22

    CPC分类号: H03K5/2481 H04L25/0292

    摘要: A data receiver and a data receiving method in which the data receiver generates two comparison signals based on amplitude modulated differential input signals, amplifies the comparison signals, compares amplified signals, and outputs logic operation results based on the amplitude modulated differential input signals and the comparison signals, thereby detecting data bits. Accordingly, the number of necessary amplifiers and comparators is reduced and a separate reference voltage generator is not needed, so that chip size reduction and low-power operation is accomplished.

    摘要翻译: 数据接收机和数据接收方法,其中数据接收机基于幅度调制的差分输入信号产生两个比较信号,放大比较信号,比较放大的信号,并基于幅度调制的差分输入信号和比较输出逻辑运算结果 信号,从而检测数据位。 因此,减少了必要的放大器和比较器的数量,并且不需要单独的参考电压发生器,从而实现了芯片尺寸减小和低功率操作。

    Data receiver and data receiving method
    5.
    发明授权
    Data receiver and data receiving method 有权
    数据接收和数据接收方式

    公开(公告)号:US07741880B2

    公开(公告)日:2010-06-22

    申请号:US11677779

    申请日:2007-02-22

    IPC分类号: H03K5/22

    CPC分类号: H03K5/2481 H04L25/0292

    摘要: A data receiver and a data receiving method in which the data receiver generates two comparison signals based on amplitude modulated differential input signals, amplifies the comparison signals, compares amplified signals, and outputs logic operation results based on the amplitude modulated differential input signals and the comparison signals, thereby detecting data bits. Accordingly, the number of necessary amplifiers and comparators is reduced and a separate reference voltage generator is not needed, so that chip size reduction and low-power operation is accomplished.

    摘要翻译: 数据接收机和数据接收方法,其中数据接收机基于幅度调制的差分输入信号产生两个比较信号,放大比较信号,比较放大的信号,并基于幅度调制的差分输入信号和比较输出逻辑运算结果 信号,从而检测数据位。 因此,减少了必要的放大器和比较器的数量,并且不需要单独的参考电压发生器,从而实现了芯片尺寸减小和低功率操作。

    High sensitivity and high dynamic-range CMOS image sensor pixel structure with dynamic C-V characteristics
    6.
    发明授权
    High sensitivity and high dynamic-range CMOS image sensor pixel structure with dynamic C-V characteristics 有权
    高灵敏度和高动态范围CMOS图像传感器像素结构具有动态C-V特性

    公开(公告)号:US07781719B2

    公开(公告)日:2010-08-24

    申请号:US11463679

    申请日:2006-08-10

    IPC分类号: H01J40/14 H03F3/08

    摘要: A new photogate pixel structure for high performance CMOS Image Sensors is proposed. A new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance characteristics, which can be controlled by varying the control-voltage at the photogate node. Since the sensitivity is inversely proportional to the integration capacitance, the dynamic integration capacitance characteristics can provide the new functionality and controllability for high sensitivity and high dynamic range. At a low voltage level of the photogate, the pixel sensitivity of the new photogate pixel structure is maximized due to the minimum value of the integration capacitance. At a high voltage of the photogate, the dynamic range of the new structure can be maximized due to the increased well capacity. In addition, at an optimum bias voltage of the photogate, both the dynamic-range and the sensitivity can be simultaneously improved. Consequently, the new pixel structure allows performance tunability as well as optimization in both the dynamic range and the sensitivity of the image sensor cell.

    摘要翻译: 提出了一种用于高性能CMOS图像传感器的新型光栅像素结构。 新的光栅结构被并入到光电二极管有源像素结构中。 所提出的像素结构表现出动态积分电容特性,其可以通过改变光栅节点处的控制电压来控制。 由于灵敏度与积分电容成反比,动态积分电容特性可为高灵敏度和高动态范围提供新的功能和可控性。 在光栅的低电压电平下,由于积分电容的最小值,新的光栅像素结构的像素灵敏度最大化。 在光栅的高电压下,由于井容量的增加,新结构的动态范围可以最大化。 另外,在光栅的最佳偏置电压下,可以同时提高动态范围和灵敏度。 因此,新的像素结构允许性能可调性以及图像传感器单元的动态范围和灵敏度的优化。

    SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof
    8.
    发明申请
    SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof 失效
    SET / RESET锁存电路,施密特触发电路和基于MOBILE的D型触发器电路及其分频器电路

    公开(公告)号:US20070069810A1

    公开(公告)日:2007-03-29

    申请号:US11418207

    申请日:2006-05-05

    摘要: The present invention relates to SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. Herein, SET/RESET latch circuit is especially configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied for very high speed digital circuits A SET/RESET latch circuit, characterized by including a transistor 1 and 2 in which each emitter of said transistors is commonly connected to a current source, and a negative differential resistance diode 1 and 2 which are respectively connected to each collector of said transistor 1 and 2; and additionally performing to be the relationship of IP

    摘要翻译: 本发明涉及使用SET / RESET锁存电路和施密特触发电路的SET / RESET锁存电路,施密特触发电路和基于MOBILE的D型触发器电路和分频器电路。 这里,SET / RESET锁存电路特别配置有CML型晶体管和负差分电阻二极管。 SET / RESET锁存电路可以应用于非常高速的数字电路A SET / RESET锁存电路,其特征在于包括晶体管1和2,其中所述晶体管的每个发射极共同连接到电流源,负差分电阻 二极管1和2分别连接到所述晶体管1和2的每个集电极; 并且另外执行以下的关系:其中,I P :所述负差分电阻二极管1和2的峰值电流为:与所述晶体管1和2的发射极的公共节点串联连接的电流源的电流; 从而在分别在所述晶体管1和2的基端口上提供归零模式SET和RESET电压的情况下提供单个和差分非归零模式输出。