摘要:
A new photogate pixel structure for high performance CMOS Image Sensors is proposed. A new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance characteristics, which can be controlled by varying the control-voltage at the photogate node. Since the sensitivity is inversely proportional to the integration capacitance, the dynamic integration capacitance characteristics can provide the new functionality and controllability for high sensitivity and high dynamic range. At a low voltage level of the photogate, the pixel sensitivity of the new photogate pixel structure is maximized due to the minimum value of the integration capacitance. At a high voltage of the photogate, the dynamic range of the new structure can be maximized due to the increased well capacity. In addition, at an optimum bias voltage of the photogate, both the dynamic-range and the sensitivity can be simultaneously improved. Consequently, the new pixel structure allows performance tunability as well as optimization in both the dynamic range and the sensitivity of the image sensor cell.
摘要:
A new photogate pixel structure for high performance CMOS Image Sensors is proposed. A new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance characteristics, which can be controlled by varying the control-voltage at the photogate node. Since the sensitivity is inversely proportional to the integration capacitance, the dynamic integration capacitance characteristics can provide the new functionality and controllability for high sensitivity and high dynamic range. At a low voltage level of the photogate, the pixel sensitivity of the new photogate pixel structure is maximized due to the minimum value of the integration capacitance. At a high voltage of the photogate, the dynamic range of the new structure can be maximized due to the increased well capacity. In addition, at an optimum bias voltage of the photogate, both the dynamic-range and the sensitivity can be simultaneously improved. Consequently, the new pixel structure allows performance tunability as well as optimization in both the dynamic range and the sensitivity of the image sensor cell.
摘要:
The new RTD-HBT differential oscillator circuit topology is proposed. At the nodes of the inductors and varactors in the conventional differential oscillator topology, each the RTD is attached to increase the magnitude of the negative conductance, which results in performance improvement in both the RF output power and phase noise. And, the differential sinusoidal voltage waveform which is essential for the wireless communication system are generated. In addition, the DC power consumption RTD-HBT differential oscillator circuit is similar to the conventional HBT differential oscillator due to the small DC power consumption performance of the RTD.
摘要:
A data receiver and a data receiving method in which the data receiver generates two comparison signals based on amplitude modulated differential input signals, amplifies the comparison signals, compares amplified signals, and outputs logic operation results based on the amplitude modulated differential input signals and the comparison signals, thereby detecting data bits. Accordingly, the number of necessary amplifiers and comparators is reduced and a separate reference voltage generator is not needed, so that chip size reduction and low-power operation is accomplished.
摘要:
A data receiver and a data receiving method in which the data receiver generates two comparison signals based on amplitude modulated differential input signals, amplifies the comparison signals, compares amplified signals, and outputs logic operation results based on the amplitude modulated differential input signals and the comparison signals, thereby detecting data bits. Accordingly, the number of necessary amplifiers and comparators is reduced and a separate reference voltage generator is not needed, so that chip size reduction and low-power operation is accomplished.
摘要:
A new photogate pixel structure for high performance CMOS Image Sensors is proposed. A new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance characteristics, which can be controlled by varying the control-voltage at the photogate node. Since the sensitivity is inversely proportional to the integration capacitance, the dynamic integration capacitance characteristics can provide the new functionality and controllability for high sensitivity and high dynamic range. At a low voltage level of the photogate, the pixel sensitivity of the new photogate pixel structure is maximized due to the minimum value of the integration capacitance. At a high voltage of the photogate, the dynamic range of the new structure can be maximized due to the increased well capacity. In addition, at an optimum bias voltage of the photogate, both the dynamic-range and the sensitivity can be simultaneously improved. Consequently, the new pixel structure allows performance tunability as well as optimization in both the dynamic range and the sensitivity of the image sensor cell.
摘要:
The present invention relates to a SET/RESET latch circuit a Schmitt trigger circuit, and a MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. The SET/RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied to very high speed digital circuits.
摘要翻译:本发明涉及使用SET / RESET锁存电路和施密特触发电路的SET / RESET锁存电路,施密特触发电路和基于MOBILE的D型触发电路和分频器电路。 SET / RESET锁存电路配置有CML型晶体管和负差分电阻二极管。 SET / RESET锁存电路可以应用于非常高速的数字电路。
摘要:
The present invention relates to SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. Herein, SET/RESET latch circuit is especially configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied for very high speed digital circuits A SET/RESET latch circuit, characterized by including a transistor 1 and 2 in which each emitter of said transistors is commonly connected to a current source, and a negative differential resistance diode 1 and 2 which are respectively connected to each collector of said transistor 1 and 2; and additionally performing to be the relationship of IP
摘要翻译:本发明涉及使用SET / RESET锁存电路和施密特触发电路的SET / RESET锁存电路,施密特触发电路和基于MOBILE的D型触发器电路和分频器电路。 这里,SET / RESET锁存电路特别配置有CML型晶体管和负差分电阻二极管。 SET / RESET锁存电路可以应用于非常高速的数字电路A SET / RESET锁存电路,其特征在于包括晶体管1和2,其中所述晶体管的每个发射极共同连接到电流源,负差分电阻 二极管1和2分别连接到所述晶体管1和2的每个集电极; 并且另外执行以下的关系:其中,I sub> P SUB >:所述负差分电阻二极管1和2的峰值电流为:与所述晶体管1和2的发射极的公共节点串联连接的电流源的电流; 从而在分别在所述晶体管1和2的基端口上提供归零模式SET和RESET电压的情况下提供单个和差分非归零模式输出。