公开(公告)号：US07781719B2

公开(公告)日：2010-08-24

申请号：US11463679

申请日：2006-08-10

申请人： Kyoung-Hoon Yang ,  Sung-Sik Lee

发明人： Kyoung-Hoon Yang ,  Sung-Sik Lee

IPC分类号： H01J40/14 ,  H03F3/08

CPC分类号： H01L27/14609 ,  H01L27/14643 ,  H04N5/3559

摘要： A new photogate pixel structure for high performance CMOS Image Sensors is proposed. A new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance characteristics, which can be controlled by varying the control-voltage at the photogate node. Since the sensitivity is inversely proportional to the integration capacitance, the dynamic integration capacitance characteristics can provide the new functionality and controllability for high sensitivity and high dynamic range. At a low voltage level of the photogate, the pixel sensitivity of the new photogate pixel structure is maximized due to the minimum value of the integration capacitance. At a high voltage of the photogate, the dynamic range of the new structure can be maximized due to the increased well capacity. In addition, at an optimum bias voltage of the photogate, both the dynamic-range and the sensitivity can be simultaneously improved. Consequently, the new pixel structure allows performance tunability as well as optimization in both the dynamic range and the sensitivity of the image sensor cell.

摘要翻译： 提出了一种用于高性能CMOS图像传感器的新型光栅像素结构。 新的光栅结构被并入到光电二极管有源像素结构中。 所提出的像素结构表现出动态积分电容特性，其可以通过改变光栅节点处的控制电压来控制。 由于灵敏度与积分电容成反比，动态积分电容特性可为高灵敏度和高动态范围提供新的功能和可控性。 在光栅的低电压电平下，由于积分电容的最小值，新的光栅像素结构的像素灵敏度最大化。 在光栅的高电压下，由于井容量的增加，新结构的动态范围可以最大化。 另外，在光栅的最佳偏置电压下，可以同时提高动态范围和灵敏度。 因此，新的像素结构允许性能可调性以及图像传感器单元的动态范围和灵敏度的优化。

公开(公告)号：US07573310B2

公开(公告)日：2009-08-11

申请号：US11418207

申请日：2006-05-05

申请人： Kyoung-Hoon Yang ,  Tae-Ho Kim ,  Yongsik Jeong

发明人： Kyoung-Hoon Yang ,  Tae-Ho Kim ,  Yongsik Jeong

IPC分类号： H03K3/315

CPC分类号： H03K3/315 ,  H03K3/2885 ,  H03K3/2897 ,  H03K5/00006 ,  H03K17/58

摘要： The present invention relates to a SET/RESET latch circuit a Schmitt trigger circuit, and a MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. The SET/RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied to very high speed digital circuits.

摘要翻译： 本发明涉及使用SET / RESET锁存电路和施密特触发电路的SET / RESET锁存电路，施密特触发电路和基于MOBILE的D型触发电路和分频器电路。 SET / RESET锁存电路配置有CML型晶体管和负差分电阻二极管。 SET / RESET锁存电路可以应用于非常高速的数字电路。

公开(公告)号：US20070069810A1

公开(公告)日：2007-03-29

申请号：US11418207

申请日：2006-05-05

申请人： Kyoung-Hoon Yang ,  Tae-Ho Kim

发明人： Kyoung-Hoon Yang ,  Tae-Ho Kim

IPC分类号： H03B7/06 ,  H03K17/58 ,  H03K19/10 ,  H03K19/02 ,  G06F17/50

CPC分类号： H03K3/315 ,  H03K3/2885 ,  H03K3/2897 ,  H03K5/00006 ,  H03K17/58

摘要： The present invention relates to SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. Herein, SET/RESET latch circuit is especially configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied for very high speed digital circuits A SET/RESET latch circuit, characterized by including a transistor 1 and 2 in which each emitter of said transistors is commonly connected to a current source, and a negative differential resistance diode 1 and 2 which are respectively connected to each collector of said transistor 1 and 2; and additionally performing to be the relationship of IP

摘要翻译： 本发明涉及使用SET / RESET锁存电路和施密特触发电路的SET / RESET锁存电路，施密特触发电路和基于MOBILE的D型触发器电路和分频器电路。 这里，SET / RESET锁存电路特别配置有CML型晶体管和负差分电阻二极管。 SET / RESET锁存电路可以应用于非常高速的数字电路A SET / RESET锁存电路，其特征在于包括晶体管1和2，其中所述晶体管的每个发射极共同连接到电流源，负差分电阻 二极管1和2分别连接到所述晶体管1和2的每个集电极; 并且另外执行以下的关系：其中，I P ：所述负差分电阻二极管1和2的峰值电流为：与所述晶体管1和2的发射极的公共节点串联连接的电流源的电流; 从而在分别在所述晶体管1和2的基端口上提供归零模式SET和RESET电压的情况下提供单个和差分非归零模式输出。

公开(公告)号：US20080029795A1

公开(公告)日：2008-02-07

申请号：US11624592

申请日：2007-01-18

申请人： Kyoung-Hoon Yang ,  Sung Sik Lee

发明人： Kyoung-Hoon Yang ,  Sung Sik Lee

IPC分类号： H01L31/062

CPC分类号： H01L27/14609 ,  H01L27/14643 ,  H04N5/3559

摘要： A new photogate pixel structure for high performance CMOS Image Sensors is proposed. A new photogate structure is incorporated into the photodiode active-pixel structure. The proposed pixel structure exhibits the dynamic integration capacitance characteristics, which can be controlled by varying the control-voltage at the photogate node. Since the sensitivity is inversely proportional to the integration capacitance, the dynamic integration capacitance characteristics can provide the new functionality and controllability for high sensitivity and high dynamic range. At a low voltage level of the photogate, the pixel sensitivity of the new photogate pixel structure is maximized due to the minimum value of the integration capacitance. At a high voltage of the photogate, the dynamic range of the new structure can be maximized due to the increased well capacity. In addition, at an optimum bias voltage of the photogate, both the dynamic-range and the sensitivity can be simultaneously improved. Consequently, the new pixel structure allows performance tunability as well as optimization in both the dynamic range and the sensitivity of the image sensor cell.

摘要翻译： 提出了一种用于高性能CMOS图像传感器的新型光栅像素结构。 新的光栅结构被并入到光电二极管有源像素结构中。 所提出的像素结构表现出动态积分电容特性，其可以通过改变光栅节点处的控制电压来控制。 由于灵敏度与积分电容成反比，动态积分电容特性可为高灵敏度和高动态范围提供新的功能和可控性。 在光栅的低电压电平下，由于积分电容的最小值，新的光栅像素结构的像素灵敏度最大化。 在光栅的高电压下，由于井容量的增加，新结构的动态范围可以最大化。 另外，在光栅的最佳偏置电压下，可以同时提高动态范围和灵敏度。 因此，新的像素结构允许性能可调性以及图像传感器单元的动态范围和灵敏度的优化。

公开(公告)号：US07573343B2

公开(公告)日：2009-08-11

申请号：US11463669

申请日：2006-08-10

申请人： Kyoung-Hoon Yang ,  Sun-Kyu Choi ,  Yongsik Jeong

发明人： Kyoung-Hoon Yang ,  Sun-Kyu Choi ,  Yongsik Jeong

IPC分类号： H03B7/14 ,  H03K3/315

CPC分类号： H03B7/08 ,  H01L27/0605 ,  H01L29/7371 ,  H01L29/882 ,  H01L29/93 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1231 ,  H03B5/1243

摘要： The new RTD-HBT differential oscillator circuit topology is proposed. At the nodes of the inductors and varactors in the conventional differential oscillator topology, each the RTD is attached to increase the magnitude of the negative conductance, which results in performance improvement in both the RF output power and phase noise. And, the differential sinusoidal voltage waveform which is essential for the wireless communication system are generated. In addition, the DC power consumption RTD-HBT differential oscillator circuit is similar to the conventional HBT differential oscillator due to the small DC power consumption performance of the RTD.

摘要翻译： 提出了新的RTD-HBT差分振荡器电路拓扑结构。 在常规差分振荡器拓扑中的电感器和变容二极管的节点处，每个RTD被连接以增加负电导的幅度，这导致RF输出功率和相位噪声两者的性能提高。 并且，产生对于无线通信系统必不可少的差分正弦电压波形。 此外，直流功耗RTD-HBT差分振荡电路由于RTD的小直流功耗特性，与传统的HBT差分振荡器相似。

公开(公告)号：US20090080465A1

公开(公告)日：2009-03-26

申请号：US11943074

申请日：2007-11-20

申请人： Kyoung Hoon YANG ,  Tae Ho KIM

发明人： Kyoung Hoon YANG ,  Tae Ho KIM

IPC分类号： H04J3/04 ,  H03K19/173

CPC分类号： H03K19/1738 ,  H04J3/047

摘要： Disclosed herein is a multiplexer circuit. The multiplexer circuit includes a first differential output unit, a second differential output unit, and a selection unit. The first differential output unit receives NRZ input signals (D1, and D1) and a clock signal (CLK), and generates differential RZ-mode outputs (R1 and R1). The second differential output unit receives NRZ input signals (D2 and D2) and an inverted clock signal ( CLK), and generates differential RZ-mode outputs (R2 and R2). The selection unit receives the RZ-mode output signals (R1, R1, R2, and R2) generated at the first differential output unit and the second differential output unit, and generates NRZ mode outputs in each half cycle of the clock signal (CLK).

摘要翻译： 这里公开了一种多路复用器电路。 多路复用器电路包括第一差分输出单元，第二差分输出单元和选择单元。 第一差分输出单元接收NRZ输入信号（D1和 D1）和时钟信号（CLK），并产生差分RZ模式输出（R1和 R1 ）。 第二差分输出单元接收NRZ输入信号（D2和 D2）和反相时钟信号（“ostst =”single“> CLK）），并产生差分RZ模式输出（R2和< o ostyle =“single”> R2）。 选择单元接收在第一差分输出单元和第二差分输出单元处产生的RZ模式输出信号（R1， R1，R2和 R2） 并在时钟信号（CLK）的每个半周期内产生NRZ模式输出。

公开(公告)号：US20090039236A1

公开(公告)日：2009-02-12

申请号：US11859086

申请日：2007-09-21

申请人： Kyoung Hoon YANG ,  Ha Jun LEE

发明人： Kyoung Hoon YANG ,  Ha Jun LEE

IPC分类号： H01L27/146

CPC分类号： H01L27/14609 ,  H04N5/35518 ,  H04N5/3745

摘要： Disclosed herein is an active pixel sensor. A first transistor amplifies voltage generated in response to light at an integration node N. A second transistor is a selecting transistor, and performs a function of selecting a specific pixel from a pixel array. A third transistor resets voltage of the integration node N to voltage supplied from VDD during a reset period. A fourth transistor is a photogate, and performs a function of connecting a photogate capacitance to the integration node N, and thus increasing a dynamic range when the voltage of the integration node N is VDD−Vth (photogate: fourth transistor). A fifth transistor is a logarithmic transistor, and performs a function of generating a signal voltage in a logarithmic response to light when the voltage of the integration node N is logarithmic bias voltage−Vth (logarithmic transistor: fifth transistor); and a photodiode performs a function of converting photons into electron pairs in a depletion layer, and then causing signal charges to be accumulated when light is incident from outside.

摘要翻译： 这里公开了一种有源像素传感器。 第一晶体管放大响应于积分节点N处的光产生的电压。第二晶体管是选择晶体管，并且执行从像素阵列中选择特定像素的功能。 在复位期间，第三晶体管将积分节点N的电压复位为从VDD提供的电压。 第四晶体管是光栅，并且执行将光栅电容连接到积分节点N的功能，并且因此当积分节点N的电压为VDD-Vth（光栅：第四晶体管）时增加动态范围。 第五晶体管是对数晶体管，并且当积分节点N的电压为对数偏置电压Vth（对数晶体管：第五晶体管）时，执行产生对光对数响应的信号电压的功能; 并且光电二极管执行将光子转换成耗尽层中的电子对的功能，然后当光从外部入射时，使信号电荷累积。

公开(公告)号：US20080174343A1

公开(公告)日：2008-07-24

申请号：US11677779

申请日：2007-02-22

申请人： Young-su Cha ,  Kyoung-Hoon Yang

发明人： Young-su Cha ,  Kyoung-Hoon Yang

IPC分类号： H03K5/22

CPC分类号： H03K5/2481 ,  H04L25/0292

摘要： A data receiver and a data receiving method in which the data receiver generates two comparison signals based on amplitude modulated differential input signals, amplifies the comparison signals, compares amplified signals, and outputs logic operation results based on the amplitude modulated differential input signals and the comparison signals, thereby detecting data bits. Accordingly, the number of necessary amplifiers and comparators is reduced and a separate reference voltage generator is not needed, so that chip size reduction and low-power operation is accomplished.

摘要翻译： 数据接收机和数据接收方法，其中数据接收机基于幅度调制的差分输入信号产生两个比较信号，放大比较信号，比较放大的信号，并基于幅度调制的差分输入信号和比较输出逻辑运算结果 信号，从而检测数据位。 因此，减少了必要的放大器和比较器的数量，并且不需要单独的参考电压发生器，从而实现了芯片尺寸减小和低功率操作。

公开(公告)号：US20060132168A1

公开(公告)日：2006-06-22

申请号：US11153138

申请日：2005-06-15

申请人： Kyoung Hoon Yang ,  Sun Choi

发明人： Kyoung Hoon Yang ,  Sun Choi

IPC分类号： H03K19/195

CPC分类号： B82Y10/00 ,  H03K3/315 ,  H03K19/10

摘要： The present invention relates to CML(Current Mode Logic)-type input driving method and tunneling diode logic using MOBILE(Monostable Nistable transition Logic Element) configuration, as kinds of very high-speed digital logic circuits. The objectives of the present invention are to improve the disadvantage of MOBILE circuit configuration that is an existing tunneling diode logic, and at the same time provide new MOBILE based logic functions. Wherein, the difficulty for input voltage adjustment is resolved by replacing the input part with a CML input driving gate, and speed problem due to transistor is resolved. Moreover, a plurality of logic functions such as inverted return-to-zero D flip-flop, non-inverted return-to-zero D flip-flop, return-to-zero OR gate, return-to-zero D flip-flop generating differential output, and optical flip-flop are implemented.

摘要翻译： 本发明涉及使用MOBILE（单稳态Nistable转换逻辑元件）配置的CML（电流模式逻辑）型输入驱动方法和隧道二极管逻辑，作为非常高速数字逻辑电路的种类。 本发明的目的是改进作为现有隧道二极管逻辑的MOBILE电路配置的缺点，同时提供新的基于MOBILE的逻辑功能。 其中，通过用CML输入驱动门代替输入部分来解决输入电压调整的难度，解决晶体管导致的速度问题。 此外，还有多个逻辑功能，例如反向归零D触发器，非反相返回到零D触发器，归零或或门，归零D触发器 产生差分输出和光学触发器。

公开(公告)号：US07816972B2

公开(公告)日：2010-10-19

申请号：US11943074

申请日：2007-11-20

申请人： Kyoung Hoon Yang ,  Tae Ho Kim

发明人： Kyoung Hoon Yang ,  Tae Ho Kim

IPC分类号： H03K17/62

CPC分类号： H03K19/1738 ,  H04J3/047

摘要： Disclosed herein is a multiplexer circuit. The multiplexer circuit includes a first differential output unit, a second differential output unit, and a selection unit. The first differential output unit receives NRZ input signals (D1 and D1) and a clock signal (CLK), and generates differential RZ-mode outputs (R1 and R1). The second differential output unit receives NRZ input signals (D2 and D2) and an inverted clock signal ( CLK), and generates differential RZ-mode outputs (R2 and R2). The selection unit receives the RZ-mode output signals (R1, R1, R2, and R2) generated at the first differential output unit and the second differential output unit, and generates NRZ mode outputs in each half cycle of the clock signal (CLK).

摘要翻译： 这里公开了一种多路复用器电路。 多路复用器电路包括第一差分输出单元，第二差分输出单元和选择单元。 第一差分输出单元接收NRZ输入信号（D1和D1）和时钟信号（CLK），并产生差分RZ模式输出（R1和R1）。 第二差分输出单元接收NRZ输入信号（D2和D2）和反相时钟信号（CLK），并产生差分RZ模式输出（R2和R2）。 选择单元接收在第一差分输出单元和第二差分输出单元处产生的RZ模式输出信号（R1，R1，R2和R2），并且在时钟信号（CLK）的每个半周期中产生NRZ模式输出， 。