公开(公告)号：US20170150566A1

公开(公告)日：2017-05-25

申请号：US15313077

申请日：2015-05-20

Applicant: GERARD LIGHTING HOLDINGS PTY LTD

Inventor： James Vanderzon

IPC: H05B33/08

CPC classification number: H05B33/0845 ,  G01R19/1659 ,  G01R19/175 ,  H02M1/083 ,  H02M1/44 ,  H02M5/293 ,  H02M2001/0058 ,  H02M2005/2935 ,  H03K3/2893 ,  H03K3/2897 ,  H03K5/1536 ,  H05B33/0815 ,  H05B39/02 ,  H05B39/044 ,  Y02B70/1491

Abstract: A zero-crossing detection circuit for a trailing edge phase control dimmer circuit for controlling alternating current (AC) power to a load, wherein the circuit includes: a switching circuit for controlling delivery of AC power to the load by conducting power to the load in an ON state and not conducting power to the load in an OFF state; a switching control circuit for controlling turn-OFF and turn-ON of the switching circuit at each cycle of the AC; and a rectifier for rectifying the AC power in the non-conduction period to generate rectified dimmer voltage to be provided to the dimmer circuit, wherein the zero-crossing detection circuit includes a current sink circuit; wherein the current sink circuit has a low impedance at low instantaneous AC voltages; a comparator circuit configured to detect zero crossings of a first threshold value of the rectified dimmer voltage.

公开(公告)号：US4806791A

公开(公告)日：1989-02-21

申请号：US119080

申请日：1987-11-10

Applicant: Yasuo Mizuide

Inventor： Yasuo Mizuide

IPC: H03K3/0233 ,  H03K3/2897 ,  H03K5/24 ,  H03K5/12

CPC classification number: H03K3/2897

Abstract: A differential comparator of the hysteresis type is responsive to a high input difference voltage (V.sub.1 -V.sub.2). The comparator comprises two differential transistors; a hysteresis resistor connected between the emitters of the two transistors; current source means connected to one of the emitters of the two transistors, for determining an emitter current of the two transistors directly and via the hysteresis resistor; and an emitter current controller for controlling the emitter current of the two transistors on the basis of an output current derived from an output terminal. When a voltage difference between the two input terminals reaches a balanced hysteresis voltage value, and therefore no output current flows, the output current is sharply increased in a direction opposite to the preceding direction.

Abstract translation: 滞后类型的差分比较器响应高输入差分电压（V1-V2）。 比较器包括两个差分晶体管; 连接在两个晶体管的发射极之间的迟滞电阻器; 电流源装置连接到两个晶体管的一个发射极，用于直接和经由迟滞电阻确定两个晶体管的发射极电流; 以及发射极电流控制器，用于基于从输出端子导出的输出电流来控制两个晶体管的发射极电流。 当两个输入端子之间的电压差达到平衡滞后电压值，因此没有输出电流流过时，输出电流在与先前方向相反的方向上急剧增加。

公开(公告)号：US4554468A

公开(公告)日：1985-11-19

申请号：US510044

申请日：1983-07-01

Applicant: Robert C. Rumbaugh ,  Ira Miller

Inventor： Robert C. Rumbaugh ,  Ira Miller

IPC: H03K3/2897 ,  H03K5/24

CPC classification number: H03K3/2897

Abstract: A self latching comparator circuit has upper and lower input offset voltages associated therewith to establish hysteresis in response to a differential input signal. The comparator circuit comprises a differential amplifier adapted to receive a differential input signal and first and second parallel current mirror circuits for producing upper and lower input offset voltages when each are respectively activated. Antisaturation means are provided for preventing the current mirror circuits from saturating. An output circuit is also provided which does not load the differential output and therefore provides for a well controlled hysteresis.

Abstract translation: 自锁定比较器电路具有与其相关联的上部和下部输入偏移电压，以响应于差分输入信号建立滞后。 比较器电路包括适于接收差分输入信号的差分放大器，以及当各自分别激活时产生上和下输入偏移电压的第一和第二并联电流镜电路。 提供了抗饱和装置，用于防止电流镜电路饱和。 还提供了一个输出电路，它不加载差分输出，因此提供良好控制的滞后。

公开(公告)号：US3700924A

公开(公告)日：1972-10-24

申请号：US3700924D

申请日：1972-02-07

Applicant: HONEYWELL INC

Inventor： FULKERSON DAVID E

IPC: H03K3/26 ,  H03K3/2897 ,  H03K17/14 ,  H03K17/30 ,  H03K17/00

CPC classification number: H03K3/26 ,  H03K3/2897 ,  H03K17/14 ,  H03K17/30

Abstract: A snap-acting switching circuit having a temperature independent threshold switching voltage contains a pair of complementary transistors forming a regenerative feedback loop and a differential pair of transistors connected in one of the branches of the feedback loop to control the gain of the loop by a differential voltage.

Abstract translation: 具有温度独立阈值切换电压的快速切换电路包含形成再生反馈回路的一对互补晶体管和连接在反馈回路的一个支路中的差分晶体管对以通过差分来控制环路的增益 电压。

公开(公告)号：US3649852A

公开(公告)日：1972-03-14

申请号：US3649852D

申请日：1971-03-10

Applicant: THOMAS K BOHLEY

Inventor： BOHLEY THOMAS K

IPC: G01R13/32 ,  H03K3/037 ,  H03K3/2897 ,  H03K17/00

CPC classification number: H03K3/037 ,  G01R13/32 ,  H03K3/2897

Abstract: A triggering circuit for producing an oscilloscope sweep trigger signal employing a pair of parallel current paths, one path including one input of a first logic gate and a current control device coupled thereto and the second path including one input of a second logic gate and a second current control device coupled thereto. Feedback circuits couple the output of each gate to said input of each gate for regenerative feedback. A reset control signal is coupled to a second input of each gate. The output of said one gate is coupled to a third input of said second gate. A sync signal controls each of said current control devices to control the current through each path for operating said gates in sequence, said first gate operating at a preselected level in one half cycle of said sync signal and said second gate operating at a preselected level in the next half cycle of said sync signal to produce said triggering signal.

Abstract translation: 一种用于产生采用一对并行电流路径的示波器扫描触发信号的触发电路，一个路径包括第一逻辑门的一个输入和耦合到其的电流控制装置，第二路径包括第二逻辑门和第二逻辑门的​​一个输入 电流控制装置耦合到其上。 反馈电路将每个门的输出耦合到每个门的所述输入以用于再生反馈。 复位控制信号耦合到每个门的第二输入端。 所述一个栅极的输出耦合到所述第二栅极的第三输入端。 同步信号控制每个所述电流控制装置以控制通过每个路径的电流以顺序地操作所述门，所述第一门在所述同步信号的一个半周期中以预选电平工作，并且所述第二门在预选电平 所述同步信号的下一个半周期产生所述触发信号。

公开(公告)号：US3622805A

公开(公告)日：1971-11-23

申请号：US3622805D

申请日：1969-04-09

Applicant: HEWLETT PACKARD CO

Inventor： MCMORROW RICHARD H JR

IPC: H03K3/2897 ,  H03K3/315 ,  H03K17/00

CPC classification number: H03K3/2897 ,  H03K3/315

Abstract: A trigger circuit uses a pair of tunnel diodes- one acting as a gate and trigger element and the other acting as a control diode for the first- to generate triggering pulses. The circuit interconnections are such that the first tunnel diode provides an output gating pulse only in response to the synchronizing signal having crossed an upper threshold level provided a reset signal has occurred and the synchronizing signal has crossed a lower threshold level. This hysteresis type response to the synchronizing signal permits selective triggering of the circuit.

公开(公告)号：US3519850A

公开(公告)日：1970-07-07

申请号：US3519850D

申请日：1967-10-11

Applicant: IBM

Inventor： SMITH ROBERT

IPC: G11C11/06 ,  H03K3/2897 ,  H03F1/00 ,  H03K5/20

CPC classification number: G11C11/06007 ,  H03K3/2897

公开(公告)号：US20060214720A1

公开(公告)日：2006-09-28

申请号：US11358048

申请日：2006-02-22

Applicant: Satoshi Sobue

Inventor： Satoshi Sobue

IPC: G06F7/44 ,  G06G7/16

CPC classification number: H03K17/602 ,  H03K3/02337 ,  H03K3/2897 ,  H03K17/30

Abstract: A comparator includes a differential amplification circuit having differential input transistors and load transistors, an output transistor for outputting an output value of the comparator, a diode having a cathode connected to a ground, a current output circuit, a resistor connected between an anode of the diode and the bases of the load transistors. When the output transistor is in the OFF state, the diode clamps the voltage of the resistor to a forward voltage so that no current flows through the resistor. When the output transistor is in the ON state, the resistor has a slight voltage so that a slight current flows through the resistor. Thus, a threshold voltage of the comparator has a slight hysteresis without increase in resistance of the resistor.

Abstract translation: 比较器包括具有差分输入晶体管和负载晶体管的差分放大电路，用于输出比较器的输出值的输出晶体管，连接到地的阴极的二极管，电流输出电路，连接在 二极管和负载晶体管的基极。 当输出晶体管处于截止状态时，二极管将电阻器的电压钳位到正向电压，使得电流不流过电阻器。 当输出晶体管处于导通状态时，电阻器具有轻微的电压，从而使电流流过电阻器。 因此，比较器的阈值电压具有轻微的滞后而不增加电阻的电阻。

公开(公告)号：US4642484A

公开(公告)日：1987-02-10

申请号：US725042

申请日：1985-04-19

Applicant: Timothy J. Skovmand ,  Michael J. Mottola

Inventor： Timothy J. Skovmand ,  Michael J. Mottola

IPC: H03K3/2885 ,  H03K3/2897 ,  H03K5/153

CPC classification number: H03K3/2897 ,  H03K3/2885

Abstract: A latching comparator circuit with hysteresis, including bi-state circuit means responsive to an input signal and to a reference signal for, while in a first state, changing to a second state when the input signal has a first predetermined relationship with the reference signal, and for, while in the second state, changing to the first state when the input signal has a second predetermined relationship with the reference signal. Latch means is included for connection with the bi-state circuit means and is responsive to a control signal for preventing the bi-state circuit means from changing from one of the two states to the other of the two states after the bi-state circuit means changes to the other of the two states.

Abstract translation: 一种具有滞后的锁存比较器电路，当输入信号与参考信号具有第一预定关系时，包括响应于输入信号和参考信号的双态电路装置，当处于第一状态时，转换为第二状态， 并且当处于第二状态时，当输入信号与参考信号具有第二预定关系时，转换到第一状态。 包括锁存装置用于与双态电路装置连接，并且响应于控制信号以防止双态电路装置在双态电路装置之后从两种状态中的一种状态改变为两种状态中的另一种状态 改变了两个州的另一个。

公开(公告)号：US4485312A

公开(公告)日：1984-11-27

申请号：US387751

申请日：1982-06-11

Applicant: Hiromi Kusakabe ,  Yoshihiro Yoshida

Inventor： Hiromi Kusakabe ,  Yoshihiro Yoshida

IPC: H03K3/0233 ,  H03K3/023 ,  H03K3/2897 ,  H03K3/29 ,  H03K5/153

CPC classification number: H03K3/2897 ,  H03K3/023

Abstract: A differential pair of first and second transistors for voltage comparison is provided, and a bias circuit for setting a reference voltage is connected to the base of the second transistor. A differential pair of third and fourth transistors is provided for reference voltage switching. The third and fourth transistors have their bases connected to the collectors of the first and second transistors and their collectors connected to the bias circuit in a positive feedback relation with respect to the base of the first transistor.

Abstract translation: 提供用于电压比较的第一和第二晶体管的差分对，并且用于设置参考电压的偏置电路连接到第二晶体管的基极。 提供用于参考电压切换的第三和第四晶体管的差分对。 第三和第四晶体管的基极连接到第一和第二晶体管的集电极，并且它们的集电极以相对于第一晶体管的基极的正反馈关系连接到偏置电路。