公开(公告)号：US07881148B2

公开(公告)日：2011-02-01

申请号：US12277650

申请日：2008-11-25

申请人： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Hong-Bae Kim

发明人： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Hong-Bae Kim

IPC分类号： G11C8/00 ,  G11C8/18 ,  H03K3/017

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： A semiconductor memory device includes a clock supply portion for providing an external clock to the interior of the memory device, a clock transfer portion for transferring the clock from the clock supply portion to each of elements in the memory device and data output portions for outputting data in synchronism the clock from the clock transfer portion, wherein the clock from the clock supply portion to the clock transfer portion swings at a current mode logic (CML) level.

摘要翻译： 一种半导体存储器件，包括用于向存储器件内部提供外部时钟的时钟提供部分，用于将时钟从时钟供应部分传送到存储器件中的每个元件的时钟传送部分和用于输出数据的数据输出部分 同步来自时钟传送部分的时钟，其中从时钟提供部分到时钟传送部分的时钟以当前模式逻辑（CML）电平摆动。

公开(公告)号：US20090303827A1

公开(公告)日：2009-12-10

申请号：US12277650

申请日：2008-11-25

申请人： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Hong-Bae Kim

发明人： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Hong-Bae Kim

IPC分类号： G11C8/18

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： A semiconductor memory device includes a clock supply portion for providing an external clock to the interior of the memory device, a clock transfer portion for transferring the clock from the clock supply portion to each of elements in the memory device and data output portions for outputting data in synchronism the clock from the clock transfer portion, wherein the clock from the clock supply portion to the clock transfer portion swings at a current mode logic (CML) level.

摘要翻译： 一种半导体存储器件，包括用于向存储器件内部提供外部时钟的时钟提供部分，用于将时钟从时钟供应部分传送到存储器件中的每个元件的时钟传送部分和用于输出数据的数据输出部分 同步来自时钟传送部分的时钟，其中从时钟提供部分到时钟传送部分的时钟以当前模式逻辑（CML）电平摆动。

公开(公告)号：US20090323444A1

公开(公告)日：2009-12-31

申请号：US12277609

申请日：2008-11-25

申请人： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Bo-Kyeom Kim

发明人： Kyung-Hoon Kim ,  Sang-Sic Yoon ,  Bo-Kyeom Kim

IPC分类号： G11C7/22

CPC分类号： G11C7/1051 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225

摘要： A semiconductor memory device including a first clock transmission path configured to receive a source clock swinging at a CML level through a clock transmission line in response to an enable signal, and to convert the source clock into a clock swinging at a CMOS level. The device also includes a second clock transmission path configured to convert the source clock in a clock swinging at a CMOS level in response to the enable signal, and to output the converted clock through the clock transmission line and a data output unit configured to output data in response to output clocks of the first and second clock transmission lines.

摘要翻译： 一种半导体存储器件，包括第一时钟传输路径，其被配置为响应于使能信号通过时钟传输线接收在CML电平摆动的源时钟，并将源时钟转换为在CMOS电平摆动的时钟。 该装置还包括第二时钟传输路径，其被配置为响应于使能信号在CMOS电平摆动的时钟中转换源时钟，并且经由时钟传输线输出转换的时钟，以及配置为输出数据的数据输出单元 响应于第一和第二时钟传输线的输出时钟。

公开(公告)号：US20100308860A1

公开(公告)日：2010-12-09

申请号：US12494433

申请日：2009-06-30

申请人： Kyung-Hoon Kim ,  Sang-Sic Yoon

发明人： Kyung-Hoon Kim ,  Sang-Sic Yoon

IPC分类号： H03K17/16 ,  H03K19/0175

CPC分类号： H03K17/164 ,  H03K17/167

摘要： A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal.

摘要翻译： 半导体器件包括多个数据驱动单元，每个数据驱动单元被配置为响应于相应的数据驱动单元，通过由电源电压输入引脚提供的电源电压和通过接地电压输入引脚提供的接地电压来驱动对应的数据输出焊盘 数据代码的位;模式感测单元，被配置为感测数据代码的位模式并生成模式感测信号;以及幻影驱动单元，被配置为在电源电压输入引脚和接地电压输入之间形成电流路径 并且通过响应于图案感测信号确定的驱动力来驱动电流路径。

公开(公告)号：US07906985B2

公开(公告)日：2011-03-15

申请号：US12494433

申请日：2009-06-30

申请人： Kyung-Hoon Kim ,  Sang-Sic Yoon

发明人： Kyung-Hoon Kim ,  Sang-Sic Yoon

IPC分类号： H03K19/003 ,  H03K17/16

CPC分类号： H03K17/164 ,  H03K17/167

摘要： A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal.

摘要翻译： 半导体器件包括多个数据驱动单元，每个数据驱动单元被配置为响应于相应的数据驱动单元，通过由电源电压输入引脚提供的电源电压和通过接地电压输入引脚提供的接地电压来驱动对应的数据输出焊盘 数据代码的位;模式感测单元，被配置为感测数据代码的位模式并生成模式感测信号;以及幻影驱动单元，被配置为在电源电压输入引脚和接地电压输入之间形成电流路径 并且通过响应于图案感测信号确定的驱动力来驱动电流路径。

公开(公告)号：US07889594B2

公开(公告)日：2011-02-15

申请号：US12327312

申请日：2008-12-03

申请人： Sang-Sic Yoon ,  Kyung-Hoon Kim

发明人： Sang-Sic Yoon ,  Kyung-Hoon Kim

IPC分类号： G11C11/00

CPC分类号： G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal; a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences in response to the data division clock; a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks; and a signal transmitting unit configured to transmit an output signal of the data serializing unit to the outside.

摘要翻译： 提供一种可以减少半导体存储器件中的时钟对准训练操作所花费的时间的电路。 所述半导体存储器件包括：时钟输入单元，被配置为接收系统时钟和数据时钟; 时钟分频单元，被配置为分频数据时钟的频率以产生数据分时钟，其中所述时钟分频单元响应于反相分配控制信号确定所述数据分时钟的相位; 相位分割单元，被配置为响应于所述数据分时钟产生具有相应的预定相位差的多个多相数据分时钟; 数据串行化单元，被配置为与多个相位数据分时钟对应地串行化预定的并行模式数据; 以及信号发送单元，被配置为将数据串行化单元的输出信号发送到外部。

公开(公告)号：US07834664B2

公开(公告)日：2010-11-16

申请号：US12327112

申请日：2008-12-03

申请人： Sang-Sic Yoon ,  Kyung-Hoon Kim

发明人： Sang-Sic Yoon ,  Kyung-Hoon Kim

IPC分类号： G01R25/00 ,  H03D13/00

CPC分类号： G06F1/08

摘要： A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit configured to detect a phase of a delayed clock, which is generated by delaying the second clock by a predetermined time, on the basis of the phase of the first clock, and generate a second detection signal corresponding to a result of the detection, and a logic level determining unit configured to determine a logic level of a feedback output signal according to the first detection signal, the second detection signal and the feedback output signal.

摘要翻译： 一种半导体，包括：第一相位检测单元，被配置为基于第一时钟的相位检测第二时钟的相位，并且生成与检测结果相对应的第一检测信号;第二相位检测单元，被配置为 基于第一时钟的相位来检测通过将第二时钟延迟预定时间而产生的延迟时钟的相位，并且生成与检测结果相对应的第二检测信号，以及逻辑 电平确定单元，被配置为根据第一检测信号，第二检测信号和反馈输出信号来确定反馈输出信号的逻辑电平。

公开(公告)号：US20100054059A1

公开(公告)日：2010-03-04

申请号：US12327312

申请日：2008-12-03

申请人： Sang-Sic Yoon ,  Kyung-Hoon Kim

发明人： Sang-Sic Yoon ,  Kyung-Hoon Kim

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C8/18 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

摘要： A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal; a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences in response to the data division clock; a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks; and a signal transmitting unit configured to transmit an output signal of the data serializing unit to the outside.

摘要翻译： 提供一种可以减少半导体存储器件中的时钟对准训练操作所花费的时间的电路。 所述半导体存储器件包括：时钟输入单元，被配置为接收系统时钟和数据时钟; 时钟分频单元，被配置为分频数据时钟的频率以产生数据分时钟，其中所述时钟分频单元响应于反相分配控制信号确定所述数据分时钟的相位; 相位分割单元，被配置为响应于所述数据分时钟产生具有相应的预定相位差的多个多相数据分时钟; 数据串行化单元，被配置为与多个相位数据分时钟对应地串行化预定的并行模式数据; 以及信号发送单元，被配置为将数据串行化单元的输出信号发送到外部。

公开(公告)号：US20100007372A1

公开(公告)日：2010-01-14

申请号：US12327112

申请日：2008-12-03

申请人： Sang-Sic Yoon ,  Kyung-Hoon Kim

发明人： Sang-Sic Yoon ,  Kyung-Hoon Kim

IPC分类号： G01R31/317 ,  H03K19/00

CPC分类号： G06F1/08

摘要： A semiconductor, which includes a first phase detecting unit configured to detect a phase of a second clock on the basis of a phase of a first clock, and generate a first detection signal corresponding to a result of the detection, a second phase detecting unit configured to detect a phase of a delayed clock, which is generated by delaying the second clock by a predetermined time, on the basis of the phase of the first clock, and generate a second detection signal corresponding to a result of the detection, and a logic level determining unit configured to determine a logic level of a feedback output signal according to the first detection signal, the second detection signal and the feedback output signal.

摘要翻译： 一种半导体，包括：第一相位检测单元，被配置为基于第一时钟的相位检测第二时钟的相位，并且生成与检测结果相对应的第一检测信号;第二相位检测单元，被配置为 基于第一时钟的相位来检测通过将第二时钟延迟预定时间而产生的延迟时钟的相位，并且生成与检测结果相对应的第二检测信号，以及逻辑 电平确定单元，被配置为根据第一检测信号，第二检测信号和反馈输出信号来确定反馈输出信号的逻辑电平。

公开(公告)号：US20090168546A1

公开(公告)日：2009-07-02

申请号：US12154936

申请日：2008-05-28

申请人： Kyung-Hoon Kim ,  Sang-Sic Yoon

发明人： Kyung-Hoon Kim ,  Sang-Sic Yoon

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C8/18 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A semiconductor memory device includes a first buffering unit configured to buffer a first clock for an address signal and a command to be input in synchronization with the first clock, a second buffering unit configured to buffer a second clock for a data signal to be in synchronization with the second clock to output a buffered second clock having the same frequency as the first clock, a data output circuit configured to output an internal data in response to the buffered second clock, a delay unit configured to delay the buffered second clock by a predetermined time, and a phase detector configured to detect a phase difference of an output clock of the delay unit and the output clock of the first buffering unit, and to output the detection result.

摘要翻译： 半导体存储器件包括：第一缓冲单元，被配置为缓冲用于地址信号的第一时钟和与第一时钟同步地输入的命令;第二缓冲单元，被配置为缓冲第二时钟以使数据信号同步 第二时钟输出具有与第一时钟相同频率的缓冲的第二时钟，数据输出电路被配置为响应于所缓冲的第二时钟输出内部数据;延迟单元，被配置为将缓冲的第二时钟延迟预定的 时间，以及相位检测器，被配置为检测延迟单元的输出时钟和第一缓冲单元的输出时钟的相位差，并输出检测结果。