-
公开(公告)号:US20220068188A1
公开(公告)日:2022-03-03
申请号:US17403898
申请日:2021-08-17
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Koji HIGUCHI
IPC: G09G3/20
Abstract: A display driver is provided. A designation of an output timing at each of first and kth output channels is received, and first and second delay pulse signals are generated at respective output timings of the first and the kth output channels. First to kth first direction delay shift signals where a first delay pulse signal is present after a delay increased for each output channel from the first toward the kth output channel are generated. First to kth second direction delay shift signals where a second delay pulse signal is present after the delay increased for each output channel from the kth toward the first output channel are generated. One whose timing at which a delay pulse signal is present is earlier is selected from each of the direction delay shift signals corresponding to the same output channel, and set as first to kth output timing signals.
-
公开(公告)号:US20190392773A1
公开(公告)日:2019-12-26
申请号:US16452006
申请日:2019-06-25
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Koji HIGUCHI , Kunihiro HARAYAMA
IPC: G09G3/36 , G09G3/3258 , G02F1/1362
Abstract: A display device includes a display panel, a gate driver that supplies scan signals to a first to nth scan lines, a data driver that supplies gradation voltage signals corresponding to a video data signal to a plurality of data lines, and a display controller that supplies the video data signal to the data driver. The display controller supplies a first to nth pieces of display data to the data driver in units of display data pairs each including a kth piece of display data and an (n+1−k)th piece of display data. The gate driver supplies the scan signals to the plurality of scan lines. Each of the scan signals has different pulse widths depending on distance from the data driver to the respective first to nth scan lines. The data driver supplies the gradation voltage signals to the plurality of data lines on the basis of supply of the display data pairs from the display controller.
-
公开(公告)号:US20170110067A1
公开(公告)日:2017-04-20
申请号:US15395089
申请日:2016-12-30
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Kenichi SHIIBAYASHI , Koji HIGUCHI , Atsushi HIRAMA
IPC: G09G3/34 , G09G3/36 , G09G3/3258
CPC classification number: G09G3/3406 , G09G3/3258 , G09G3/3266 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3674 , G09G3/3685 , G09G3/3696 , G09G5/10 , G09G2300/04 , G09G2310/027 , G09G2310/0286 , G09G2310/0291 , G09G2310/0297 , G09G2310/08 , G09G2320/0247 , G09G2320/0276 , G09G2320/0626 , G09G2320/0666 , G09G2330/021 , G09G2370/08
Abstract: A source driver IC chip, designed to prevent flicker in images displayed on a display panel while suppressing power consumption and heat generation, includes: a reference gradation voltage generating part (220) configured to generate a reference gradation voltage based on a first or second gamma characteristic of the display panel, using first and second power supply voltages (VH) and (VL) inputted through first and second external terminals (PA2, PA3); and a third external terminal (PA4) for externally outputting said reference gradation voltage. The source driver IC chip further includes first and second gradation voltage generating parts configured to generate first and second gradation voltages respectively, using a reference gradation voltage based on a first gamma characteristic inputted through a fourth external terminal and a reference gradation voltage having a second gamma characteristic inputted through a fifth external terminal respectively.
-
公开(公告)号:US20160079926A1
公开(公告)日:2016-03-17
申请号:US14855376
申请日:2015-09-15
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Hiroyoshi ICHIKURA , Koji HIGUCHI
CPC classification number: G09G3/36 , H03F1/0205 , H03F1/303 , H03F3/45 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F2203/45044 , H03F2203/45116 , H03F2203/45166
Abstract: An amplifying circuit includes a first differential amplifier (first differential pair) and a second differential amplifier (second differential pair) having an input capacitance smaller than the first differential amplifier. The amplifying circuit switches between the first differential amplifier (first differential pair) and the second differential amplifier (second differential pair) in response to an amplification mode setting signal to perform amplification processing of an input signal.
Abstract translation: 放大电路包括具有小于第一差分放大器的输入电容的第一差分放大器(第一差分对)和第二差分放大器(第二差分对)。 放大电路响应于放大模式设置信号在第一差分放大器(第一差分对)和第二差分放大器(第二差分对)之间切换,以执行输入信号的放大处理。
-
公开(公告)号:US20180366077A1
公开(公告)日:2018-12-20
申请号:US16009400
申请日:2018-06-15
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Koji HIGUCHI
Abstract: Provided is a pixel drive voltage output circuit which includes: an operational amplifier ; a switching unit configured to connect a first power source line with a high-level power source terminal or a middle-level power source terminal and to connect a second power source line with the middle-level power source terminal or a low-level power source terminal; a first transistor having a first conductivity type with a first terminal connected to the first power source line, a second terminal connected to a signal output terminal, and a control terminal connected to a first output terminal of the operational amplifier; and a second transistor having a second conductivity type with a first terminal connected to the second power source line, a second terminal connected to the signal output terminal, and a control terminal connected to a second output terminal of the operational amplifier.
-
公开(公告)号:US20170011703A1
公开(公告)日:2017-01-12
申请号:US15205089
申请日:2016-07-08
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Koji HIGUCHI
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2320/0223 , G09G2320/0233
Abstract: A display device driver includes: a pixel drive voltage application unit; and a delay controller. The pixel drive voltage application unit converts a plurality of pixel data pieces into a plurality of pixel drive voltages, the pixel data pieces respectively representing luminance levels of respective pixels based on a video signal, the pixel drive voltages respectively having voltage values corresponding to the luminance levels, and applies the converted pixel drive voltages to the display device. The delay controller controls the pixel drive voltage application unit to apply the plurality of pixel drive voltages to the display device, the plurality of pixel drive voltages being sequentially delayed in units of groups, the groups each including t pixel drive voltages, and sets delay time designated by delay time designation signals as delay time to delay each of the pixel drive voltages.
Abstract translation: 显示装置驱动器包括:像素驱动电压施加单元; 和延时控制器。 像素驱动电压施加单元将多个像素数据块转换成多个像素驱动电压,分别表示基于视频信号的各像素的亮度等级的像素数据,分别具有对应于亮度的电压值的像素驱动电压 电平,并将转换的像素驱动电压施加到显示装置。 延迟控制器控制像素驱动电压施加单元将多个像素驱动电压施加到显示装置,多个像素驱动电压以组为单位顺序延迟,各组包括t个像素驱动电压,并设置延迟时间 由延迟时间指定信号指定为延迟每个像素驱动电压的延迟时间。
-
公开(公告)号:US20160307516A1
公开(公告)日:2016-10-20
申请号:US15194003
申请日:2016-06-27
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Kenichi SHIIBAYASHI , Koji HIGUCHI , Atsushi HIRAMA
IPC: G09G3/3266 , G09G3/36
CPC classification number: G09G3/3406 , G09G3/3258 , G09G3/3266 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3674 , G09G3/3685 , G09G3/3696 , G09G5/10 , G09G2300/04 , G09G2310/027 , G09G2310/0286 , G09G2310/0291 , G09G2310/0297 , G09G2310/08 , G09G2320/0247 , G09G2320/0276 , G09G2320/0626 , G09G2320/0666 , G09G2330/021 , G09G2370/08
Abstract: A source driver IC chip, designed to prevent flicker in images displayed on a display panel while suppressing power consumption and heat generation, includes: a reference gradation voltage generating part (220) configured to generate a reference gradation voltage based on a first or second gamma characteristic of the display panel, using first and second power supply voltages (VH) and (VL) inputted through first and second external terminals (PA2, PA3); and a third external terminal (PA4) for externally outputting said reference gradation voltage. The source driver IC chip further includes first and second gradation voltage generating parts configured to generate first and second gradation voltages respectively, using a reference gradation voltage based on a first gamma characteristic inputted through a fourth external terminal and a reference gradation voltage having a second gamma characteristic inputted through a fifth external terminal respectively.
-
8.
公开(公告)号:US20160071453A1
公开(公告)日:2016-03-10
申请号:US14845264
申请日:2015-09-03
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Koji HIGUCHI
CPC classification number: H03F3/393 , G09G3/20 , G09G2310/0254 , G09G2310/0291 , G09G2320/0247 , G09G2330/026 , H03F3/45183 , H03F3/45775 , H03F2200/396 , H03F2200/417 , H03F2203/45212 , H03F2203/45586 , H03F2203/45588
Abstract: When the offsets of the first and second differential units have polarities different from each other, the first and second differential units are both set to a normal connection state, i.e., a state in which the input voltage is supplied to the first input terminal of each of the first and second differential units and the output voltage is supplied to the second input terminal of each of the first and second differential units. When the offsets of the first and second differential units have the same polarity, on the other hand, the first differential unit is set to the above normal connection state and the second differential unit is set to a chopping connection state in which the output voltage is supplied to the first input terminal and the input voltage is supplied to the second input terminal.
Abstract translation: 当第一和第二差分单元的偏移具有彼此不同的极性时,第一和第二差分单元均被设置为正常连接状态,即,将输入电压提供给每个的第一输入端的状态 的第一和第二差分单元,并且输出电压被提供给第一和第二差分单元中的每一个的第二输入端子。 当第一和第二差分单元的偏移具有相同的极性时,另一方面,第一差分单元被设置为上述正常连接状态,并且第二差分单元被设置为斩波连接状态,其中输出电压为 提供给第一输入端子,并且将输入电压提供给第二输入端子。
-
公开(公告)号:US20160071479A1
公开(公告)日:2016-03-10
申请号:US14845266
申请日:2015-09-03
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Kenichi SHIIBAYASHI , Koji HIGUCHI
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G3/3688 , G09G2310/0291 , G09G2320/0223
Abstract: A driver circuit driving a display device comprises: a gradation voltage generating circuit for generating m gradation voltages (m is an integer larger than or equal to 2) indicative of m stages of gradation levels; n decoder circuits each configured to select, out of the m gradation voltages, n drive voltages (n is an integer larger than or equal to 2) corresponding to n data pieces on the basis of n input gradation signals; m gradation voltage wirings each for transferring the m gradation voltages to the n decoder circuits, respectively; and a charge supplementing circuit for supplementing each of the m gradation voltage wirings with an amount of electric charge when a voltage drop occurs in the gradation voltage wirings.
Abstract translation: 驱动显示装置的驱动电路包括:灰度电压发生电路,用于产生指示m级灰度级的m个灰度电压(m是大于或等于2的整数); n个解码器电路,每个被配置为基于n个输入灰度信号,选择m个灰度级电压中对应于n个数据的n个驱动电压(n是大于或等于2的整数) m个灰度电压配线,分别用于将m个灰度电压传送到n个解码器电路; 以及电荷补充电路,用于在灰度电压布线中发生电压降时,用m个灰度级电压配线中的每一个补充电荷量。
-
公开(公告)号:US20150287388A1
公开(公告)日:2015-10-08
申请号:US14743890
申请日:2015-06-18
Applicant: LAPIS Semiconductor Co., Ltd.
Inventor: Kenichi SHIIBAYASHI , Koji HIGUCHI , Atsushi HIRAMA
IPC: G09G5/10
CPC classification number: G09G3/3406 , G09G3/3258 , G09G3/3266 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3674 , G09G3/3685 , G09G3/3696 , G09G5/10 , G09G2300/04 , G09G2310/027 , G09G2310/0286 , G09G2310/0291 , G09G2310/0297 , G09G2310/08 , G09G2320/0247 , G09G2320/0276 , G09G2320/0626 , G09G2320/0666 , G09G2330/021 , G09G2370/08
Abstract: A source driver IC chip, designed to prevent flicker in images displayed on a display panel while suppressing power consumption and heat generation, includes: a reference gradation voltage generating part (220) configured to generate a reference gradation voltage based on a first or second gamma characteristic of the display panel, using first and second power supply voltages (VH) and (VL) inputted through first and second external terminals (PA2, PA3); and a third external terminal (PA4) for externally outputting said reference gradation voltage. The source driver IC chip further includes first and second gradation voltage generating parts configured to generate first and second gradation voltages respectively, using a reference gradation voltage based on a first gamma characteristic inputted through a fourth external terminal and a reference gradation voltage having a second gamma characteristic inputted through a fifth external terminal respectively.
Abstract translation: 一种源极驱动器IC芯片,用于在抑制功耗和发热的同时防止在显示面板上显示的图像的闪烁,包括:基准灰度电压产生部件,被配置为基于第一或第二伽玛产生参考灰度电压 使用通过第一和第二外部端子(PA2,PA3)输入的第一和第二电源电压(VH)和(VL)的显示面板的特性; 和用于从外部输出所述基准灰度电压的第三外部端子(PA4)。 源极驱动器IC芯片还包括第一和第二灰度电压产生部件,其被配置为使用基于通过第四外部端子输入的第一伽马特性的参考灰度电压和具有第二伽玛的参考灰度电压分别产生第一和第二灰度电压 分别通过第五外部端子输入的特性。
-
-
-
-
-
-
-
-
-