公开(公告)号：US09618805B2

公开(公告)日：2017-04-11

申请号：US14945669

申请日：2015-11-19

Applicant: LG Display Co., Ltd.

Inventor： Changseung Woo ,  Soonhwan Hong

IPC: G02F1/1333 ,  G02F1/1343 ,  G02F1/1339 ,  G02F1/1362 ,  G02F1/1335 ,  G02F1/1337 ,  G09G3/36

CPC classification number: G02F1/134309 ,  G02F1/133345 ,  G02F1/133512 ,  G02F1/1337 ,  G02F1/133707 ,  G02F1/133711 ,  G02F1/133788 ,  G02F1/13394 ,  G02F1/134363 ,  G02F1/136204 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/134318 ,  G02F2001/134372 ,  G09G3/3614 ,  G09G2300/0426

Abstract: A disclosed liquid crystal display includes an upper plate and a lower plate with a liquid crystal layer interposed therebetween. The display also includes a spacer positioned between the upper plate and the lower plate. The lower plate includes a lower electrode, an insulating layer over the lower electrode, an upper electrode over the insulating layer, and an alignment layer connected to the lower electrode and the upper electrode. The alignment layer is connected to the lower electrode through a hole passing through the insulating layer.

公开(公告)号：US10156747B2

公开(公告)日：2018-12-18

申请号：US14808825

申请日：2015-07-24

Applicant: LG Display Co., Ltd.

Inventor： Yousung Nam ,  Changseung Woo ,  Soonhwan Hong

IPC: G02F1/1333 ,  G02F1/1337 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1343 ,  H01L29/66 ,  G02F1/1368

Abstract: A display device optimized to operate in a low frame rate mode under certain predetermined conditions is provided. To reduce pixel discharge during the low frame rate mode, the display device employees the TFTs with metal oxide semiconductor layer, the optical alignment layer with an upper portion and a lower portion having different resistivity. In addition, a passivation layer is provided between the optical alignment layer and the pixel or the common electrode for compensating the low resistivity of the lower portion of the optical alignment layer. As such, various visual defects associated with the pixel discharge can be reduced even when the display device is operating under the low frame rate mode.

公开(公告)号：US10222671B2

公开(公告)日：2019-03-05

申请号：US15797255

申请日：2017-10-30

Applicant: LG Display Co., Ltd.

Inventor： Changseung Woo ,  Byunghyun Lee ,  Soonhwan Hong ,  Gyusik Won

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1362 ,  H01L27/12

Abstract: The present disclosure relates to a thin film transistor substrate having a color filter layer. The present disclosure provides a thin film transistor substrate comprising: a plurality of pixel areas disposed in a matrix manner on a substrate, each pixel area including an aperture area and a non-aperture area; a first color filter and a second color filter stacked at the non-aperture area on the substrate; an overcoat layer disposed on the first color filter and the second color filter; a semiconductor layer disposed at the non-aperture area on the overcoat layer; a gate insulating layer and a gate electrode stacked on a middle portion of the semiconductor layer; a third color filter at the non-aperture area on the semiconductor layer and the gate electrode; and a source electrode and a drain electrode disposed on the third color filter.

公开(公告)号：US20180120613A1

公开(公告)日：2018-05-03

申请号：US15797255

申请日：2017-10-30

Applicant: LG Display Co., Ltd.

Inventor： Changseung Woo ,  Byunghyun Lee ,  Soonhwan Hong ,  Gyusik Won

IPC: G02F1/1368 ,  H01L27/12 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/1362

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136222 ,  G02F2001/136231 ,  G02F2001/13685 ,  G02F2201/121 ,  G02F2201/123 ,  H01L27/124

Abstract: The present disclosure relates to a thin film transistor substrate having a color filter layer. The present disclosure provides a thin film transistor substrate comprising: a plurality of pixel areas disposed in a matrix manner on a substrate, each pixel area including an aperture area and a non-aperture area; a first color filter and a second color filter stacked at the non-aperture area on the substrate; an overcoat layer disposed on the first color filter and the second color filter; a semiconductor layer disposed at the non-aperture area on the overcoat layer; a gate insulating layer and a gate electrode stacked on a middle portion of the semiconductor layer; a third color filter at the non-aperture area on the semiconductor layer and the gate electrode; and a source electrode and a drain electrode disposed on the third color filter.

公开(公告)号：US10727255B2

公开(公告)日：2020-07-28

申请号：US16189688

申请日：2018-11-13

Applicant: LG Display Co., Ltd.

Inventor： Yousung Nam ,  Changseung Woo ,  Soonhwan Hong

IPC: H01L27/12 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1368 ,  H01L29/66 ,  H01L29/786

Abstract: A display device optimized to operate in a low frame rate mode under certain predetermined conditions is provided. To reduce pixel discharge during the low frame rate mode, the display device employees the TFTs with metal oxide semiconductor layer, the optical alignment layer with an upper portion and a lower portion having different resistivity. In addition, a passivation layer is provided between the optical alignment layer and the pixel or the common electrode for compensating the low resistivity of the lower portion of the optical alignment layer. As such, various visual defects associated with the pixel discharge can be reduced even when the display device is operating under the low frame rate mode.

公开(公告)号：US09741861B2

公开(公告)日：2017-08-22

申请号：US14789459

申请日：2015-07-01

Applicant: LG DISPLAY CO., LTD.

Inventor： Changseung Woo ,  Soonhwan Hong

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L27/32 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/24 ,  H01L29/66969

Abstract: A display device and a method for manufacturing the same having a thin film transistor (TFT) including a gate connected to a gate line, a drain connected to a data line, and a source connected to a pixel electrode and a passivation layer only in an opening of a pixel and a peripheral area of the TFT. The pixel electrode directly contacts the source of the TFT and overlaps the gate of the TFT.