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公开(公告)号:US10170049B2
公开(公告)日:2019-01-01
申请号:US15274003
申请日:2016-09-23
Applicant: LG Display Co., Ltd.
Inventor: Sungbin Ryu , Youngjang Lee
IPC: G09G3/3258 , G09G3/3275 , G09G3/3233 , G09G3/3266
Abstract: Provided are a display device and method of driving the same. A display device includes: a display panel including: intersecting data lines and gate lines, and pixels in a matrix, a timing controller allowing the pixels to be driven at a lower refresh rate in low-speed driving mode than in normal driving mode, and controlling a horizontal blank time to be longer in the low-speed driving mode than the normal driving mode, the horizontal blank time being a period of time during which no data voltage exists, between an nth data voltage and an (n+1)th data voltage consecutively supplied through the data lines, “n” being a positive integer, and a display panel driving circuit writing one frame of image data to the pixels during one frame period in the normal driving mode, and in a distributed manner during a second to fourth frame period in the low-speed driving mode.
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公开(公告)号:US11587509B2
公开(公告)日:2023-02-21
申请号:US17522713
申请日:2021-11-09
Applicant: LG Display Co., Ltd.
Inventor: Sungbin Ryu
IPC: G09G3/3258 , G09G3/3266 , G09G3/3275
Abstract: A display device compensates a threshold voltage Vth of a driving transistor according to a source follower internal compensation method. The threshold voltage Vth of the driving transistor is sampled in advance before one horizontal period H, so that a sufficient time for sampling the threshold voltage Vth of the driving transistor can be obtained even in a high-speed or high-resolution display device. Furthermore, the compensation rate of the internal compensation circuit is improved to reduce luminance deviation between the pixels.
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公开(公告)号:US09954014B2
公开(公告)日:2018-04-24
申请号:US15245944
申请日:2016-08-24
Applicant: LG DISPLAY CO., LTD.
Inventor: Soyoung Noh , Jinchae Jeon , Seungchan Choi , Junho Lee , Youngjang Lee , Sungbin Ryu , Kitae Kim , Bokyoung Cho , Jeanhan Yoon , Uijin Chung , Jihye Lee , Eunsung Kim , Hyunsoo Shin , Kyeongju Moon , Hyojin Kim , Wonkyung Kim , Jeihyun Lee , Soyeon Je
IPC: H01L27/12 , H01L27/32 , H01L49/02 , H01L29/417 , H01L29/786
CPC classification number: H01L27/1248 , H01L27/1225 , H01L27/1251 , H01L27/1255 , H01L27/1288 , H01L27/3258 , H01L27/3262 , H01L28/60 , H01L29/41733 , H01L29/78675 , H01L29/7869
Abstract: A thin film transistor substrate having two different types of thin film transistors on the same substrate, and a display using the same are discussed. The thin film transistor substrate can include a substrate, a first thin film transistor (TFT), a second TFT, a first storage capacitor electrode, an oxide layer, a nitride layer, a second storage capacitor electrode, a planar layer and a pixel electrode. The first TFT is disposed in a first area, the second TFT is disposed in a second area, and the first storage capacitor electrode is disposed in a third area on the substrate respectively. The oxide layer covers the first and second TFTs, and exposes the first storage capacitor electrode. The nitride layer is disposed on the oxide layer and covers the first storage capacitor electrode. The second storage capacitor electrode overlaps with the first storage capacitor electrode on the nitride layer. The planar layer covers the first and second TFTs, and the second storage capacitor electrode. The pixel electrode is disposed on the planar layer.
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公开(公告)号:US20170092198A1
公开(公告)日:2017-03-30
申请号:US15274003
申请日:2016-09-23
Applicant: LG Display Co., Ltd.
Inventor: Sungbin Ryu , Youngjang Lee
IPC: G09G3/3258 , G09G3/3275 , G09G3/3233 , G09G3/3266
CPC classification number: G09G3/3258 , G09G3/3233 , G09G3/3266 , G09G3/3275 , G09G2300/0426 , G09G2300/0452 , G09G2300/0814 , G09G2300/0819 , G09G2310/0224 , G09G2310/0251 , G09G2310/0286 , G09G2310/08 , G09G2320/0214 , G09G2320/0247 , G09G2330/021 , G09G2330/022 , G09G2340/0435
Abstract: Provided are a display device and method of driving the same. A display device includes: a display panel including: intersecting data lines and gate lines, and pixels in a matrix, a timing controller allowing the pixels to be driven at a lower refresh rate in low-speed driving mode than in normal driving mode, and controlling a horizontal blank time to be longer in the low-speed driving mode than the normal driving mode, the horizontal blank time being a period of time during which no data voltage exists, between an nth data voltage and an (n+1)th data voltage consecutively supplied through the data lines, “n” being a positive integer, and a display panel driving circuit writing one frame of image data to the pixels during one frame period in the normal driving mode, and in a distributed manner during a second to fourth frame period in the low-speed driving mode.
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