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    Phase error compensation circuit
    1.
    发明授权
    Phase error compensation circuit 有权
    相位误差补偿电路

    公开(公告)号：US09479142B1

    公开(公告)日：2016-10-25

    申请号：US14806478

    申请日：2015-07-22

    Applicant: Linear Technology Corporation

    Inventor： John Perry Myers

    IPC: H03K5/13 ,  H03H11/18 ,  H03K5/02 ,  H03K5/26 ,  H03H11/22 ,  H03K5/00

    CPC classification number: H03H11/18 ,  H03B27/00 ,  H03D3/009 ,  H03D7/1441 ,  H03D7/1458 ,  H03D2200/0021 ,  H03D2200/0043 ,  H03H11/22 ,  H03K5/02 ,  H03K5/26 ,  H03K2005/00286

    Abstract: A method and system of compensating for phase error. A phase error compensation circuit is configured to generate a phase-corrected quadrature Q output signal and a corresponding phase-corrected in-phase I output signal, the circuit includes a first transconductance circuit configured to convert a voltage signal related to an I input voltage signal to an I current signal. A second transconductance circuit is configured to convert a voltage signal related to a Q input signal to a Q current signal. A first multiplier circuit is configured to multiply the Q current signal times a Q scaling constant. A second multiplier circuit is configured to multiply the I current signal times an I scaling constant. An I summer sums the I current signal with the scaled Q signal. A Q summer sums the Q current signal with the scaled I signal.

    Abstract translation: 一种补偿相位误差的方法和系统。 相位误差补偿电路被配置为产生相位校正的正交Q输出信号和对应的相位校正的同相I输出信号，该电路包括第一跨导电路，其被配置为将与I输入电压信号相关的电压信号 到I当前信号。 第二跨导电路被配置为将与Q输入信号相关的电压信号转换为Q电流信号。 第一乘法器电路被配置为将Q电流信号乘以Q缩放常数。 第二乘法器电路被配置为将I电流信号乘以I缩放常数。 I夏天用缩放的Q信号来计算I电流信号。 Q夏天与缩放的I信号相加Q电流信号。

    Level-shifting amplifier
    2.
    发明授权
    Level-shifting amplifier 有权
    电平转换放大器

    公开(公告)号：US09374050B1

    公开(公告)日：2016-06-21

    申请号：US14610597

    申请日：2015-01-30

    Applicant: LINEAR TECHNOLOGY CORPORATION

    Inventor： Joseph Adut ,  John Perry Myers

    IPC: H03F3/45

    CPC classification number: H03F3/45502 ,  H03F3/45201 ,  H03F2203/45081 ,  H03F2203/45082

    Abstract: A differential amplifier may, when connected to a positive or negative supply voltage and to a ground voltage, provide a differential pair of outputs signals at a differential output that are an amplification of a differential pair of input signals at a differential input. A differential input stage may receive the differential pair of input signals from the differential input and may include a first transistor associated with one of the input signals and a second transistor associated with the other input signal. A differential output stage may generate the differential pair of output signals at the differential output and may include a third transistor associated with one of the output signals and a fourth transistor associated with the other output signal. The first, second, third, and fourth transistors may be all P type or all N type. The differential pair of output signals may have a common mode that is: near the ground voltage when the first, second, third, and fourth transistors are all N type and the supply voltage is positive with respect to the ground voltage; near the supply voltage when the first, second, third, and fourth transistors are all P type and the supply voltage is positive with respect to the ground voltage; near the ground voltage when the first, second, third, and fourth transistors are all P type and the supply voltage is negative with respect to the ground voltage; or near the supply voltage when the first, second, third, and fourth transistors are all N type and the supply voltage is negative with respect to the ground voltage.

    Abstract translation: 当差分放大器连接到正或负电源电压和接地电压时，可以在差分输出端提供差分输出信号差分输出信号，差分输出信号是差分输入端的差分输入信号对的放大。 差分输入级可以接收来自差分输入的差分输入信号对，并且可以包括与输入信号之一相关联的第一晶体管和与另一输入信号相关联的第二晶体管。 差分输出级可以在差分输出处产生差分输出信号对，并且可以包括与输出信号之一相关联的第三晶体管和与另一输出信号相关联的第四晶体管。 第一，第二，第三和第四晶体管可以是全P型或全N型。 输出信号的差分对可以具有共模，即当第一，第二，第三和第四晶体管都为N型时，接地电压附近，并且电源电压相对于接地电压为正; 当第一，第二，第三和第四晶体管都为P型并且电源电压相对于接地电压为正时在电源电压附近; 当第一，第二，第三和第四晶体管都为P型并且电源电压相对于接地电压为负时，接地电压附近; 或者当第一，第二，第三和第四晶体管都为N型并且电源电压相对于接地电压为负时，接近电源电压。

    DISTORTION COMPENSATION CIRCUIT
    4.
    发明申请
    DISTORTION COMPENSATION CIRCUIT 有权
    失真补偿电路

    公开(公告)号：US20160248617A1

    公开(公告)日：2016-08-25

    申请号：US14806492

    申请日：2015-07-22

    Applicant: Linear Technology Corporation

    Inventor： John Perry Myers

    IPC: H04L27/36 ,  H04B1/04

    CPC classification number: H04L27/364 ,  H03C2200/0083 ,  H03D3/009 ,  H03D2200/0088 ,  H03F1/3211 ,  H03F1/3247 ,  H03F3/4508 ,  H03F3/45475 ,  H04B1/1036 ,  H04B3/32 ,  H04L25/03343 ,  H04L27/368

    Abstract: A method and system of compensating for distortion in a baseband in-phase (I) and a corresponding baseband quadrature (Q) signal. The circuit includes an in-phase I attenuator configured to attenuate the baseband in-phase I signal and an in-phase Q attenuator configured to attenuate the baseband Q signal. There are one or more circuits that are configured to receive the attenuated in-phase I signal and the attenuated baseband Q signal. Each circuit performs a different calculation based on predetermined equations configured to determine the IM2, HD2@0°, HD2@90°, IM3@0°, IM3@90°, HD3@0°, and HD3@90°. The distortion compensation circuit is configured to use the result of at least one of the calculation circuits to generate I and Q distortion compensation signals.

    Abstract translation: 补偿基带同相（I）和对应的基带正交（Q）信号中的失真的方法和系统。 该电路包括被配置为衰减基带同相I信号的同相I衰减器和被配置为衰减基带Q信号的同相Q衰减器。 存在被配置为接收衰减的同相I信号和衰减的基带Q信号的一个或多个电路。 每个电路根据预定的方程式执行不同的计算，该方程式被配置为确定IM2，HD2 @ 0°，HD2 @ 90°，IM3 @ 0°，IM3 @ 90°，HD3 @ 0°和HD3 @ 90°。 失真补偿电路被配置为使用至少一个计算电路的结果来产生I和Q失真补偿信号。

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