公开(公告)号：US08875071B2

公开(公告)日：2014-10-28

申请号：US13904202

申请日：2013-05-29

Applicant: LSI Corporation

Inventor： Hai Wang ,  Joseph Garofalo ,  Barry L. Bartholomew ,  Liu Ming Xu ,  Han Jun Zhang ,  You Xin Rao ,  Qin Xie

IPC: G06F9/45 ,  G06F9/455 ,  G06F17/50 ,  G11C27/04

CPC classification number: G06F17/5045 ,  G06F2217/14 ,  G11C19/28

Abstract: An automated method is provided for designing an integrated circuit. A net list of an integrated circuit design is generated, wherein the net list includes a scan chain having a sequence of individual scan cells. A sequence of two or more individual scan cells of the scan chain is identified as a candidate for replacement by a custom shift array macro cell. The identified sequence of two or more individual scan cells is then replaced with a custom shift array macro cell that provides a functionally equivalent shift function as the replaced sequence of two or more individual scan cells. The custom shift array macro cell includes only two input pins and one output pin.

Abstract translation: 提供了一种用于设计集成电路的自动化方法。 生成集成电路设计的网络列表，其中网络列表包括具有单独扫描单元的序列的扫描链。 扫描链的两个或多个单独的扫描单元的序列被识别为用于由自定义移位阵列宏小区替换的候选。 然后用自定义移位阵列宏小区替换两个或更多个单个扫描单元的识别序列，其提供功能等同的移位函数作为两个或更多个单独扫描单元的替换序列。 自定义移位阵列宏单元仅包含两个输入引脚和一个输出引脚。

公开(公告)号：US08745558B1

公开(公告)日：2014-06-03

申请号：US13755869

申请日：2013-01-31

Applicant: LSI Corporation

Inventor： Joseph Garofalo ,  Barry L. Bartholomew ,  Mujiang Luo ,  You Xin Rao

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5045

Abstract: A method is provided for designing an integrated circuit. The method includes generating a net list of an integrated circuit design, wherein the net list includes one or more component cells selected from a cell library. The component cells include transmission gate logic cells and sourcing cells that drive the transmission gate logic cells. Each transmission gate logic cell has an associated timing model with a timing characteristic defined as a function of a driving strength attribute of a sourcing cell used to characterize the transmission gate logic cell. The method further includes auditing the net list to determine if a given sourcing cell in the integrated circuit design has a sufficient driving strength based at least on the driving strength attribute of a transmission gate logic cell being driven by the given sourcing cell.

Abstract translation: 提供了一种用于设计集成电路的方法。 该方法包括生成集成电路设计的网络列表，其中网络列表包括从单元库选择的一个或多个组件单元。 组件单元包括传输门逻辑单元和驱动传输门逻辑单元的源单元。 每个传输门逻辑单元具有相关联的定时模型，定时特性被定义为用于表征传输门逻辑单元的源单元的驱动强度属性的函数。 该方法还包括审核网络列表以确定集成电路设计中的给定采购单元是否具有足够的驱动强度，至少基于由给定采购单元驱动的传输门逻辑单元的驱动强度属性。

公开(公告)号：US20140270050A1

公开(公告)日：2014-09-18

申请号：US13904202

申请日：2013-05-29

Applicant: LSI Corporation

Inventor： Hai Wang ,  Joseph Garofalo ,  Barry L. Bartholomew ,  Liu Ming Xu ,  Han Jun Zhang ,  You Xin Rao ,  Qin Xie

IPC: G06F17/50 ,  G11C27/04

CPC classification number: G06F17/5045 ,  G06F2217/14 ,  G11C19/28

Abstract: An automated method is provided for designing an integrated circuit. A net list of an integrated circuit design is generated, wherein the net list includes a scan chain having a sequence of individual scan cells. A sequence of two or more individual scan cells of the scan chain is identified as a candidate for replacement by a custom shift array macro cell. The identified sequence of two or more individual scan cells is then replaced with a custom shift array macro cell that provides a functionally equivalent shift function as the replaced sequence of two or more individual scan cells. The custom shift array macro cell includes only two input pins and one output pin.

Abstract translation: 提供了一种用于设计集成电路的自动化方法。 生成集成电路设计的网络列表，其中网络列表包括具有单独扫描单元的序列的扫描链。 扫描链的两个或多个单独的扫描单元的序列被识别为用于由自定义移位阵列宏小区替换的候选。 然后用自定义移位阵列宏小区替换两个或更多个单个扫描单元的识别序列，其提供功能等同的移位函数作为两个或更多个单独扫描单元的替换序列。 自定义移位阵列宏单元仅包含两个输入引脚和一个输出引脚。

公开(公告)号：US20140181570A1

公开(公告)日：2014-06-26

申请号：US13724946

申请日：2012-12-21

Applicant: LSI CORPORATION

Inventor： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

IPC: G06F1/06

CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/206

Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

Abstract translation: 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。

公开(公告)号：US08773799B1

公开(公告)日：2014-07-08

申请号：US13724946

申请日：2012-12-21

Applicant: LSI Corporation

Inventor： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

IPC: G11B5/09

CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/206

Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

Abstract translation: 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。