公开(公告)号：US20150070796A1

公开(公告)日：2015-03-12

申请号：US14031990

申请日：2013-09-19

Applicant: LSI Corporation

Inventor： George Mathew ,  Nayak Ratnakar Aravind ,  Suharli Tedja

IPC: G11B20/10

CPC classification number: G11B20/10046 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10222 ,  G11B20/10527

Abstract: A magnetic recording system includes an array of analog inputs operable to receive an array of analog signals retrieved from a magnetic storage medium, where one of the array of analog signals corresponds with a reference channel, a timing recovery circuit operable to generate a clock signal based on the analog signal for the reference channel, a number of analog to digital converters each operable to sample one of the array of analog signals based on the clock signal to yield a number of digital channels, and a joint equalizer operable to filter the digital channels to yield an equalized output.

Abstract translation: 磁记录系统包括一组模拟输入，可操作用于接收从磁存储介质检索的模拟信号阵列，其中模拟信号阵列之一对应于参考通道，定时恢复电路可操作以产生基于时钟信号 对于参考通道的模拟信号，多个模数转换器，每个转换器可操作以基于时钟信号对模拟信号阵列中的一个进行采样以产生多个数字通道;以及联合均衡器，可操作以对数字通道进行滤波 以产生均衡的输出。

公开(公告)号：US09129646B2

公开(公告)日：2015-09-08

申请号：US14031990

申请日：2013-09-19

Applicant: LSI Corporation

Inventor： George Mathew ,  Nayak Ratnakar Aravind ,  Suharli Tedja

IPC: G11B5/00 ,  G11B20/10 ,  G11B5/09 ,  G11B5/012

CPC classification number: G11B20/10046 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10222 ,  G11B20/10527

Abstract: A magnetic recording system includes an array of analog inputs operable to receive an array of analog signals retrieved from a magnetic storage medium, where one of the array of analog signals corresponds with a reference channel, a timing recovery circuit operable to generate a clock signal based on the analog signal for the reference channel, a number of analog to digital converters each operable to sample one of the array of analog signals based on the clock signal to yield a number of digital channels, and a joint equalizer operable to filter the digital channels to yield an equalized output.

Abstract translation: 磁记录系统包括一组模拟输入，可操作用于接收从磁存储介质检索的模拟信号阵列，其中模拟信号阵列之一对应于参考通道，定时恢复电路可操作以产生基于时钟信号 对于参考通道的模拟信号，多个模数转换器，每个转换器可操作以基于时钟信号对模拟信号阵列中的一个进行采样以产生多个数字通道;以及联合均衡器，可操作以对数字通道进行滤波 以产生均衡的输出。

公开(公告)号：US08773799B1

公开(公告)日：2014-07-08

申请号：US13724946

申请日：2012-12-21

Applicant: LSI Corporation

Inventor： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

IPC: G11B5/09

CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/206

Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

Abstract translation: 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。

公开(公告)号：US09129650B2

公开(公告)日：2015-09-08

申请号：US14021811

申请日：2013-09-09

Applicant: LSI Corporation

Inventor： George Mathew ,  Bruce Wilson ,  Suharli Tedja ,  Eui Seok Hwang

IPC: G11B20/06 ,  G11B5/09 ,  G11B5/035 ,  G11B5/02 ,  G11B20/10

CPC classification number: G11B20/10268 ,  G11B20/10009 ,  G11B20/10046

Abstract: A magnetic recording system includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, a modulator operable to combine the analog signals to yield a frequency division multiplexed signal, a demodulator operable to yield a plurality of demodulated signals from the frequency division multiplexed signal corresponding to each channel of the array, and a joint equalizer operable to filter the plurality of demodulated signals to yield an equalized output.

Abstract translation: 磁记录系统包括可操作以接收从磁存储介质检索的模拟信号的模拟输入阵列，可操作以组合模拟信号以产生频分多路复用信号的调制器，解调器，可操作以产生来自 对应于阵列的每个通道的频分多路复用信号，以及联合均衡器，可操作以对多个解调信号进行滤波以产生均衡的输出。

公开(公告)号：US20150029608A1

公开(公告)日：2015-01-29

申请号：US14021811

申请日：2013-09-09

Applicant: LSI Corporation

Inventor： George Mathew ,  Bruce Wilson ,  Suharli Tedja ,  Eui Seok Hwang

IPC: G11B20/10

CPC classification number: G11B20/10268 ,  G11B20/10009 ,  G11B20/10046

Abstract: A magnetic recording system includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, a modulator operable to combine the analog signals to yield a frequency division multiplexed signal, a demodulator operable to yield a plurality of demodulated signals from the frequency division multiplexed signal corresponding to each channel of the array, and a joint equalizer operable to filter the plurality of demodulated signals to yield an equalized output.

Abstract translation: 磁记录系统包括可操作以接收从磁存储介质检索的模拟信号的模拟输入阵列，可操作以组合模拟信号以产生频分多路复用信号的调制器，解调器，可操作以产生来自 对应于阵列的每个通道的频分多路复用信号，以及联合均衡器，可操作以对多个解调信号进行滤波以产生均衡的输出。

公开(公告)号：US20140181570A1

公开(公告)日：2014-06-26

申请号：US13724946

申请日：2012-12-21

Applicant: LSI CORPORATION

Inventor： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

IPC: G06F1/06

CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/206

Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

Abstract translation: 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。