Vector Processor Having Instruction Set With Sliding Window Non-Linear Convolutional Function
    1.
    发明申请
    Vector Processor Having Instruction Set With Sliding Window Non-Linear Convolutional Function 有权
    具有滑动窗口非线性卷积函数的指令集的向量处理器

    公开(公告)号:US20140317163A1

    公开(公告)日:2014-10-23

    申请号:US14168615

    申请日:2014-01-30

    Abstract: A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.

    Abstract translation: 提供具有具有滑动窗非线性卷积函数的指令集的处理器。 处理器获得对多个输入延迟信号样本执行非线性卷积函数的软件指令。 响应于用于非线性卷积函数的软件指令,处理器生成两个或更多个输入延迟信号样本的加权和,其中加权和包括被定义为一个或多个非线性卷积的和的多个可变系数, 输入延迟信号采样幅度的线性函数; 并重复所述生成步骤,用于输入延迟信号采样的至少一个时移版本,以计算多个连续输出。 用于非线性卷积函数的软件指令可选地是处理器的指令集的一部分。 非线性卷积函数可以对具有存储器的非线性系统进行建模,例如功率放大器模型和/或数字预失真功能。

    PREAMBLE DETECTION USING VECTOR PROCESSORS
    2.
    发明申请
    PREAMBLE DETECTION USING VECTOR PROCESSORS 有权
    使用矢量处理器的前瞻性检测

    公开(公告)号:US20140064338A1

    公开(公告)日:2014-03-06

    申请号:US13800167

    申请日:2013-03-13

    CPC classification number: H04B1/709 H04B1/7113

    Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.

    Abstract translation: 在一个实施例中,可编程向量处理器在无线通信网络中执行前导码检测。 矢量处理器中的前导码检测的实现可以通过一组向量指令成为可能的,该矢量指令包括(i)用于加载接收数据的向量的循环加载指令,(ii)将接收到的数据的向量与 扰码以同时产生多个复相关,(iii)用于排列复数相关的向量的部分转置指令,供快速哈达马变换(FHT)处理器使用,以及(iv)用于对FHT处理执行FHT处理的FHT指令 复杂相关的向量。 在矢量处理器中实现前同步码检测允许更多的接收数据被同时处理。 结果,本公开的前同步码检测器可以使用比使用硬件加速器实现的可比较的前同步码检测器更少的时钟周期来检测前同步码。

    CHUNK-BASED DOUBLE-DWELL PREAMBLE DETECTION
    3.
    发明申请
    CHUNK-BASED DOUBLE-DWELL PREAMBLE DETECTION 有权
    基于CHUNK的双重DWE前缀检测

    公开(公告)号:US20130279404A1

    公开(公告)日:2013-10-24

    申请号:US13686205

    申请日:2012-11-27

    CPC classification number: H04W8/18 H04B1/70775

    Abstract: In one embodiment, the invention is a method for performing preamble detection in a wireless communication network. The method performs a first dwell, wherein non-overlapping chunks of received data are processed to generate partial correlation values for each possible combination of a signature code and delay. Candidate selection is performed by comparing each of the partial correlation values to a candidate-selection threshold. For each detected candidate, the chunks of received data are processed to generate full correlation values. Each full correlation value is then compared to a preamble-detection threshold to detect a transmitted signature. Generating full correlation values for only the selected candidates reduces the computation complexity over prior-art methods that generate full correlation values for all signatures at all delays.

    Abstract translation: 在一个实施例中,本发明是一种在无线通信网络中执行前导码检测的方法。 该方法执行第一驻留,其中处理接收数据的非重叠块以产生签名代码和延迟的每个可能组合的部分相关值。 通过将每个部分相关值与候选选择阈值进行比较来执行候选选择。 对于每个检测到的候选,处理接收数据的块以产生完全相关值。 然后将每个完全相关值与前导码检测阈值进行比较以检测发送的签名。 仅为所选择的候选者生成完全相关值降低了在所有延迟下为所有签名产生完全相关值的现有技术的计算复杂度。

    Chunk-based double-dwell preamble detection
    8.
    发明授权
    Chunk-based double-dwell preamble detection 有权
    基于块的双驻区前导码检测

    公开(公告)号:US08804672B2

    公开(公告)日:2014-08-12

    申请号:US13686205

    申请日:2012-11-27

    CPC classification number: H04W8/18 H04B1/70775

    Abstract: In one embodiment, the invention is a method for performing preamble detection in a wireless communication network. The method performs a first dwell, wherein non-overlapping chunks of received data are processed to generate partial correlation values for each possible combination of a signature code and delay. Candidate selection is performed by comparing each of the partial correlation values to a candidate-selection threshold. For each detected candidate, the chunks of received data are processed to generate full correlation values. Each full correlation value is then compared to a preamble-detection threshold to detect a transmitted signature. Generating full correlation values for only the selected candidates reduces the computation complexity over prior-art methods that generate full correlation values for all signatures at all delays.

    Abstract translation: 在一个实施例中,本发明是一种在无线通信网络中执行前导码检测的方法。 该方法执行第一驻留,其中处理接收数据的非重叠块以产生签名代码和延迟的每个可能组合的部分相关值。 通过将每个部分相关值与候选选择阈值进行比较来执行候选选择。 对于每个检测到的候选,处理接收数据的块以产生完全相关值。 然后将每个完全相关值与前导码检测阈值进行比较以检测发送的签名。 仅为所选择的候选者生成完全相关值降低了在所有延迟下为所有签名产生完全相关值的现有技术的计算复杂度。

Patent Agency Ranking