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    Vector Processor Having Instruction Set With Sliding Window Non-Linear Convolutional Function
    1.
    发明申请
    Vector Processor Having Instruction Set With Sliding Window Non-Linear Convolutional Function 有权
    具有滑动窗口非线性卷积函数的指令集的向量处理器

    公开(公告)号：US20140317163A1

    公开(公告)日：2014-10-23

    申请号：US14168615

    申请日：2014-01-30

    申请人： LSI Corporation

    发明人： Kameran Azadet ,  Joseph Williams ,  Meng-Lin Yu

    IPC分类号： G06F17/15

    CPC分类号： H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

    摘要： A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.

    摘要翻译： 提供具有具有滑动窗非线性卷积函数的指令集的处理器。 处理器获得对多个输入延迟信号样本执行非线性卷积函数的软件指令。 响应于用于非线性卷积函数的软件指令，处理器生成两个或更多个输入延迟信号样本的加权和，其中加权和包括被定义为一个或多个非线性卷积的和的多个可变系数， 输入延迟信号采样幅度的线性函数; 并重复所述生成步骤，用于输入延迟信号采样的至少一个时移版本，以计算多个连续输出。 用于非线性卷积函数的软件指令可选地是处理器的指令集的一部分。 非线性卷积函数可以对具有存储器的非线性系统进行建模，例如功率放大器模型和/或数字预失真功能。

    Modeling of a Target Volterra Series Using an Orthogonal Parallel Wiener Decomposition
    4.
    发明申请
    Modeling of a Target Volterra Series Using an Orthogonal Parallel Wiener Decomposition 有权
    使用正交并行Wiener分解建模目标Volterra系列

    公开(公告)号：US20140314182A1

    公开(公告)日：2014-10-23

    申请号：US14255499

    申请日：2014-04-17

    申请人： LSI Corporation

    发明人： Kameran Azadet

    IPC分类号： H04B1/04

    CPC分类号： H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

    摘要： Improved techniques are provided for modeling a target Volterra series using an orthogonal parallel Weiner decomposition. A target Volterra Series is modeled by obtaining the target Volterra Series V comprised of a plurality of terms up to degree K; providing a parallel Wiener decomposition representing the target Volterra Series V, wherein the parallel Wiener decomposition is comprised of a plurality of linear filters in series with at least one corresponding static non-linear function, wherein an input signal is applied to the plurality of linear filters and wherein outputs of the non-linear functions are linearly combined to produce an output of the parallel Wiener decomposition; computing a matrix C. for a given degree up to the degree K, wherein a given row of the matrix C corresponds to one of the linear filters and is obtained by enumerating monomial cross-products of coefficients of the corresponding linear filter for the given degree; and determining filter coefficients for at least one of the plurality of linear filters, such that the rows of the matrix C are linearly independent.

    摘要翻译： 提供了改进的技术，用于使用正交并行的维纳分解对目标沃尔泰拉系列进行建模。 目标Volterra系列通过获得包含多达K度的术语的目标Volterra系列V进行建模; 提供表示目标Volterra系列V的并行维纳分解，其中所述并行维纳分解由与至少一个对应的静态非线性函数串联的多个线性滤波器组成，其中输入信号被施加到所述多个线性滤波器 并且其中所述非线性函数的输出被线性组合以产生所述并行维纳分解的输出; 计算矩阵C.给定的度数直到K度，其中矩阵C的给定行对应于线性滤波器中的一个，并且通过枚举给定度的相应线性滤波器的系数的单项式乘积获得 ; 以及确定所述多个线性滤波器中的至少一个的滤波器系数，使得所述矩阵C的行是线性独立的。

    SWITCHING POWER AMPLIFIER SYSTEM FOR MULTI-PATH SIGNAL INTERLEAVING
    5.
    发明申请
    SWITCHING POWER AMPLIFIER SYSTEM FOR MULTI-PATH SIGNAL INTERLEAVING 有权
    切换功率放大器系统进行多路信号交互

    公开(公告)号：US20140159991A1

    公开(公告)日：2014-06-12

    申请号：US13709743

    申请日：2012-12-10

    申请人： LSI CORPORATION

    发明人： Peter Kiss ,  Said E. Abdelli ,  Kameran Azadet ,  Donald R. Laturell ,  James F. MacDonald ,  Ross S. Wilson

    IPC分类号： H03F1/00 ,  H03H11/00 ,  H01Q23/00

    CPC分类号： H03H11/00 ,  H03F3/2175 ,  H03F3/24 ,  H03M3/50

    摘要： A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal.

    摘要翻译： 一种用于多径信号交织的开关功率放大器包括：信号分配器，被配置为将来自数字源的多位源信号分离成多个多位信号;一个或多个分数延迟滤波器，被配置为延迟一个或多个信号 所述多个信号经过选定的时间，多个比特流转换器，每个比特流转换器被配置为接收所述多比特信号中的一个，每个比特流转换器还被配置为基于所述多比特信号生成单比特信号 接收的多位信号，多个开关功率放大器，每个开关功率放大器被配置为从位流转换器之一接收单位信号;以及交织器，被配置为通过交织两个或多个输出 开关功率放大器，其中交织器的交错输出的采样频率大于所选择的多位源信号的采样频率。

    Maximum Likelihood Bit-Stream Generation and Detection Using M-Algorithm and Infinite Impulse Response Filtering
    6.
    发明申请
    Maximum Likelihood Bit-Stream Generation and Detection Using M-Algorithm and Infinite Impulse Response Filtering 有权
    使用M算法和无限脉冲响应滤波的最大似然比特流生成和检测

    公开(公告)号：US20140086367A1

    公开(公告)日：2014-03-27

    申请号：US14090555

    申请日：2013-11-26

    申请人： LSI Corporation

    发明人： Kameran Azadet ,  Steven C. Pinault

    IPC分类号： H04L25/03 ,  H04L1/00

    CPC分类号： G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

    摘要： Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal.

    摘要翻译： 使用M算法和无限脉冲响应（IIR）滤波提供最大似然比特流生成和检测技术。 将M算法应用于目标输入信号X以对目标输入信号X执行最大似然序列估计，以产生数字比特流B，使得在通过IIR滤波器滤波之后，产生的数字流Y产生误差信号 满足一个或多个预定义的要求。 预定义的要求包括例如基本上最小的误差。 在示例性比特检测实现中，目标输入信号X包括观察到的模拟信号，并且所产生的数字流Y包括与发送的比特流相对应的接收信道的数字化输出。 在示例性比特流生成实现中，目标输入信号X包括期望的发射信号，并且所产生的数字流Y包括所需发射信号的估计。

    Method and apparatus for high density pulse density modulation
    8.
    发明授权
    Method and apparatus for high density pulse density modulation 有权
    用于高密度脉冲密度调制的方法和装置

    公开(公告)号：US08995521B2

    公开(公告)日：2015-03-31

    申请号：US13663534

    申请日：2012-10-30

    申请人： LSI Corporation

    发明人： Donald R. Laturell ,  Said E. Abdelli ,  Peter Kiss ,  James F. MacDonald ,  Ross S. Wilson ,  Kameran Azadet

    IPC分类号： H03K7/04 ,  H04L27/04 ,  H03M5/04 ,  H03G11/00

    CPC分类号： H04L27/04 ,  H03F3/217 ,  H03F3/24 ,  H03F3/60 ,  H03G11/002 ,  H03M5/04

    摘要： A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can be combined again to reconstruct the original function. The method in accordance with the present disclosure limits the amount of input power necessary to achieve higher output power, lowers operating voltage and improves power amplifier efficiency.

    摘要翻译： 公开了一种用于高密度脉冲密度调制的方法和系统。 根据本公开，使用互补的一对非线性函数将调制功能分为两个频带限制流。 更具体地，一个比特流定义包含原始功能的峰值，而另一个比特流包含原始比特流的软限幅版本。 比特流被施加到一对开关放大器，并且可以再次组合比特流以重建原始功能。 根据本公开的方法限制了实现更高输出功率所需的输入功率量，降低了工作电压并提高了功率放大器的效率。

    Hybrid digital/analog power amplifier
    9.
    发明授权
    Hybrid digital/analog power amplifier 有权
    混合数字/模拟功率放大器

    公开(公告)号：US08908798B2

    公开(公告)日：2014-12-09

    申请号：US13729231

    申请日：2012-12-28

    申请人： LSI Corporation

    发明人： Ross S. Wilson ,  Said E. Abdelli ,  Peter Kiss ,  Kameran Azadet ,  Donald R. Laturell ,  James F. MacDonald

    IPC分类号： H04L27/00 ,  H03F3/38 ,  H03F3/189 ,  H03F3/217

    CPC分类号： H03F3/38 ,  H03F3/189 ,  H03F3/217

    摘要： The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA.

    摘要翻译： 本发明可以体现在使用混合模拟/数字RF架构的射频功率放大器（RF-PA）预驱动电路中，所述混合模拟/数字RF架构包括重新同步的数模转换器，以驱动适于驱动标准高功率放大器的高效大功率输出级 （HPA）输出设备。 混合模拟/数字RF架构保留了传统S类架构中高数字内容集成的优点，同时放松了对输出晶体管和位流发生器的性能要求。 所得到的预驱动电路将数字设计的VLSI集成优势与模拟设计特有的任意输出功率电平的可扩展性相结合。 混合模拟/数字驱动电路非常适用于无线通信系统中使用的模拟和Class-S HPA，例如Doherty型HPA。

    Digital Processor Having Instruction Set with Complex Angle Function
    10.
    发明申请
    Digital Processor Having Instruction Set with Complex Angle Function 有权
    具有复角函数的指令集的数字处理器

    公开(公告)号：US20140317376A1

    公开(公告)日：2014-10-23

    申请号：US14255491

    申请日：2014-04-17

    申请人： LSI Corporation

    发明人： Kameran Azadet

    IPC分类号： G06F9/30

    CPC分类号： H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

    摘要： A digital processor, such as a vector processor or a scalar processor, is provided having an instruction set with a complex angle function. A complex angle is evaluated for an input value, x, by obtaining one or more complex angle software instructions having the input value, x, as an input; in response to at least one of the complex angle software instructions, performing the following steps: invoking at least one complex angle functional unit that implements the one or more complex angle software instructions to apply the complex angle function to the input value, x; and generating an output corresponding to the complex angle of the input value, x, using one or more multipliers of a Multiply Accumulate (MAC) unit of the digital processor, wherein the complex angle software instruction is part of an instruction set of the digital signal processor. Multiplication operations optionally employ one or more multipliers of the MAC unit of the digital processor.

    摘要翻译： 提供数字处理器，例如矢量处理器或标量处理器，其具有具有复角函数的指令集。 通过获得具有输入值x的一个或多个复杂角软件指令作为输入，对输入值x评估复角度; 响应于所述复杂角度软件指令中的至少一个，执行以下步骤：调用实现所述一个或多个复杂角度软件指令的至少一个复角函数单元以将所述复角函数应用于所述输入值x; 以及使用所述数字处理器的乘法累积（MAC）单元的一个或多个乘法器生成与所述输入值x的复角相对应的输出，其中所述复合角软件指令是所述数字信号的指令集的一部分 处理器。 乘法运算可选地采用数字处理器的MAC单元的一个或多个乘法器。