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公开(公告)号：US20220102208A1
公开(公告)日：2022-03-31
申请号：US17497702
申请日：2021-10-08
发明人： Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号： H01L21/768 , H01L21/285 , H01L21/321 , H01L21/324 , H01L27/11524 , H01L27/11556 , C23C16/04 , C23C16/50 , C23C16/00
摘要： Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
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公开(公告)号：US20200185273A1
公开(公告)日：2020-06-11
申请号：US16793464
申请日：2020-02-18
发明人： Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号： H01L21/768 , C23C16/00 , C23C16/50 , C23C16/04 , H01L27/11556 , H01L27/11524 , H01L21/324 , H01L21/321 , H01L21/285
摘要： Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
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公开(公告)号：US20180277431A1
公开(公告)日：2018-09-27
申请号：US15991413
申请日：2018-05-29
发明人： Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号： H01L21/768 , H01L21/285 , C23C16/00 , H01L21/321 , H01L21/324 , C23C16/04 , C23C16/50 , H01L27/11524 , H01L27/11556
摘要： Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
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公开(公告)号：US20160093528A1
公开(公告)日：2016-03-31
申请号：US14866621
申请日：2015-09-25
发明人： Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号： H01L21/768 , H01L27/115 , H01L21/324 , H01L23/48 , H01L21/285 , H01L21/321
CPC分类号： H01L21/76879 , C23C16/00 , C23C16/045 , C23C16/50 , H01L21/28556 , H01L21/321 , H01L21/324 , H01L21/76856 , H01L21/76861 , H01L21/76876 , H01L21/76898 , H01L27/11524 , H01L27/11556 , H01L2924/0002 , H01L2924/00
摘要： Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
摘要翻译： 这里描述的是用钨填充特征的方法，以及涉及抑制钨成核的相关系统和装置。 在一些实施方案中，所述方法涉及沿特征轮廓的选择性抑制。 选择性地抑制钨成核的方法可以包括将特征暴露于直接或远程等离子体。 使用预抑制和抑制后处理来调节抑制效果，通过在宽的工艺窗口中的抑制促进特征填充。 本文描述的方法可用于填充诸如钨通孔的垂直特征，以及诸如垂直NAND（VNAND）字线的水平特征。 这些方法可以用于适形填充和自下而上/内向外填充。 应用实例包括逻辑和存储器接触填充，DRAM掩埋字线填充，垂直集成存储器栅极和字线填充，以及使用硅通孔的3-D集成。
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公开(公告)号：US10580695B2
公开(公告)日：2020-03-03
申请号：US15991413
申请日：2018-05-29
发明人： Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号： H01L21/768 , H01L21/285 , H01L21/321 , H01L21/324 , H01L27/11524 , H01L27/11556 , C23C16/04 , C23C16/50 , C23C16/00
摘要： Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
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公开(公告)号：US09997405B2
公开(公告)日：2018-06-12
申请号：US14866621
申请日：2015-09-25
发明人： Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号： H01L21/44 , H01L21/768 , H01L21/285 , H01L21/321 , H01L21/324 , H01L27/11524 , H01L27/11556 , C23C16/00 , C23C16/04 , C23C16/50
CPC分类号： H01L21/76879 , C23C16/00 , C23C16/045 , C23C16/50 , H01L21/28556 , H01L21/321 , H01L21/324 , H01L21/76856 , H01L21/76861 , H01L21/76876 , H01L21/76898 , H01L27/11524 , H01L27/11556 , H01L2924/0002 , H01L2924/00
摘要： Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
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