公开(公告)号：US20050038977A1

公开(公告)日：2005-02-17

申请号：US10940268

申请日：2004-09-13

申请人： Andrew Glew ,  Larry Mennemeier ,  Alexander Peleg ,  David Bistry ,  Millind Mittal ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan ,  Derrick Lin ,  Ramamohan Vakkalagadda

发明人： Andrew Glew ,  Larry Mennemeier ,  Alexander Peleg ,  David Bistry ,  Millind Mittal ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan ,  Derrick Lin ,  Ramamohan Vakkalagadda

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/455 ,  G06F9/46

CPC分类号： G06F9/3017 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30189 ,  G06F9/384 ,  G06F9/462

摘要： A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number of physical registers appear to software as a single software-visible register file. The decode/execution unit is to execute on the contents of the single software-visible register file instructions of a first instruction type and of a second instruction type, wherein the single software-visible register file is to be operated as a flat register file during execution of instructions of the second instruction type and as a stack referenced register file during execution of instructions of the first instruction type.

摘要翻译： 具有对存储在单个逻辑寄存器文件中的不同数据类型进行操作的指令的处理器。 根据本发明的一个实施例，处理器包括多个物理寄存器，存储器单元和解码/执行单元。 存储单元是将物理寄存器的数量作为单个软件可见的寄存器文件显示在软件上。 解码/执行单元执行第一指令类型和第二指令类型的单个软件可见寄存器文件指令的内容，其中单个软件可见寄存器文件将作为平坦寄存器文件操作 在执行第一指令类型的指令期间执行第二指令类型的指令和作为堆栈引用的寄存器堆栈。

公开(公告)号：US6036350A

公开(公告)日：2000-03-14

申请号：US859013

申请日：1997-05-20

申请人： Larry Mennemeier ,  Alexander Peleg ,  Carole Dulong ,  Millind Mittal ,  Benny Eitan ,  Eiichi Kowashi

发明人： Larry Mennemeier ,  Alexander Peleg ,  Carole Dulong ,  Millind Mittal ,  Benny Eitan ,  Eiichi Kowashi

IPC分类号： G06F7/544 ,  G06F7/00 ,  G06F7/02 ,  G06F7/50

CPC分类号： G06F7/544 ,  G06F2207/3828 ,  G06F2207/5442

摘要： A technique for sorting packed signed numbers of two operands into maxima and minima operands and solving absolute differences for each pair of corresponding values of maxima and minima. After packing two source operands with a plurality of data elements containing signed values, a greater-than comparison operation is performed on each pair of corresponding numbers in the two operands to determine which is greater. An exclusive-OR mask is generated for use in swapping those values which need to be rearranged so that all maxima are in one operand and all minima are in another operand. Once the sorting of maxima and minima is complete, a packed subtraction operation is then performed by subtracting the minima from corresponding maxima to obtain absolute differences.

摘要翻译： 一种用于将两个操作数的有符号数目的最大值和最小值操作数进行排序并解决每一对最大值和最小值对应值的绝对差异的技术。 在包含具有包含有符号值的多个数据元素的两个源操作数之后，对两个操作数中的每对相应数字执行大于比较的操作，以确定哪个更大。 生成异或掩码以用于交换需要重新排列的那些值，使得所有最大值都在一个操作数中，并且所有最小值都在另一个操作数中。 一旦最大值和最小值的分类完成，则通过从相应的最大值中减去最小值来进行压缩减法运算，以获得绝对差。

公开(公告)号：US6128614A

公开(公告)日：2000-10-03

申请号：US246575

申请日：1999-02-08

申请人： Larry Mennemeier ,  Alexander Peleg ,  Carole Dulong ,  Millind Mittal ,  Benny Eitan ,  Eiichi Kowashi

发明人： Larry Mennemeier ,  Alexander Peleg ,  Carole Dulong ,  Millind Mittal ,  Benny Eitan ,  Eiichi Kowashi

IPC分类号： G06F7/24 ,  G06F9/30 ,  G06F9/302 ,  G06F17/30

CPC分类号： G06F9/30014 ,  G06F7/24 ,  G06F9/30021 ,  G06F9/30036 ,  Y10S707/99936 ,  Y10S707/99937

摘要： A technique for sorting packed numbers of two operands into minima or maxima operand with their indices to identify the origin of those selected values. After packing two source operands with a plurality of data elements containing numerical values, greater-than comparison operation is performed on the two operands to generate a mask. The mask is used to identify those corresponding pair of data elements of the first and second operands which need to be passed through the subsequent stages in order to generate a sorted minima or maxima. The operands are AND'ed with the mask or the complement of the mask to generate the required minima/maxima result. The same AND'ing technique is used with two other operands containing indices of the values in the first two operands. The indices identify the originating location of the sorted maxima/minima.

摘要翻译： 一种用于将两个操作数的打包数分成最小值或最大值操作数的技术，其索引用于标识这些选定值的起始点。 在使用包含数值的多个数据元素打包两个源操作数之后，对两个操作数进行大于比较的操作以生成掩码。 掩模用于识别需要通过后续阶段的第一和第二操作数的相应数据元素对，以便生成排序的最小值或最大值。 操作数与掩码或掩码的补码进行“和”生成所需的最小/最大值结果。 使用与前两个操作数中包含值的两个其他操作数相同的AND'ing技术。 这些索引标识了排序最大值/最小值的起始位置。

公开(公告)号：US5907842A

公开(公告)日：1999-05-25

申请号：US575606

申请日：1995-12-20

申请人： Larry Mennemeier ,  Alexander Peleg ,  Carole Dulong ,  Millind Mittal ,  Benny Eitan ,  Eiichi Kowashi

发明人： Larry Mennemeier ,  Alexander Peleg ,  Carole Dulong ,  Millind Mittal ,  Benny Eitan ,  Eiichi Kowashi

IPC分类号： G06F7/24 ,  G06F9/30 ,  G06F9/302 ,  G06F17/30

CPC分类号： G06F9/30014 ,  G06F7/24 ,  G06F9/30021 ,  G06F9/30036 ,  Y10S707/99936 ,  Y10S707/99937

摘要： A technique for sorting packed numbers of two operands into minima or maxima operand with their indices to identify the origin of those selected values. After packing two source operands with a plurality of data elements containing numerical values, greater-than comparison operation is performed on the two operands to generate a mask. The mask is used to identify those corresponding pair of data elements of the first and second operands which need to be passed through the subsequent stages in order to generate a sorted minima or maxima. The operands are AND'ed with the mask or the complement of the mask to generate the required minima/maxima result. The same AND'ing technique is used with two other operands containing indices of the values in the first two operands. The indices identify the originating location of the sorted maxima/minima.

公开(公告)号：US5983256A

公开(公告)日：1999-11-09

申请号：US960413

申请日：1997-10-29

申请人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

发明人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf Witt

IPC分类号： G06F7/48 ,  G06F7/52 ,  G06F7/533 ,  G06F7/544 ,  G06F9/302 ,  G06F15/78 ,  G06F17/14 ,  G06F17/16 ,  G06T1/20 ,  G06F7/38 ,  G06F7/00 ,  G06F15/00

CPC分类号： G06F7/60 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F7/4812 ,  G06F7/5324 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06T1/20 ,  G06F2207/3828 ,  G06F7/49921 ,  G06F7/5338

摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

摘要翻译： 一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。 在一个实施例中，处理器耦合到存储器。 存储器中存储有第一打包数据和第二打包数据。 处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。 该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

公开(公告)号：US20130091190A1

公开(公告)日：2013-04-11

申请号：US13633086

申请日：2012-10-01

申请人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

发明人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

IPC分类号： G06F7/60

CPC分类号： G06F7/60 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

公开(公告)号：US5721892A

公开(公告)日：1998-02-24

申请号：US554625

申请日：1995-11-06

申请人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Wolf Witt ,  Carole Dulong ,  Eiichi Kowashi

发明人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Wolf Witt ,  Carole Dulong ,  Eiichi Kowashi

IPC分类号： G06F7/544 ,  G06F7/38

CPC分类号： G06F9/30036 ,  G06F7/5443 ,  G06F2207/3828

摘要： A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least one of the data elements in this third packed data storing the result of performing a multiply-subtract operation on data elements in the first and second packed data.

摘要翻译： 一种用于在处理器中包括用于对压缩数据进行乘法减法操作的指令的方法和装置。 在一个实施例中，处理器耦合到存储器。 存储器中存储有第一打包数据和第二打包数据。 处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。 该第三打包数据中的至少一个数据元素存储对第一和第二打包数据中的数据元素进行乘法运算的结果。

公开(公告)号：US08396915B2

公开(公告)日：2013-03-12

申请号：US13603370

申请日：2012-09-04

申请人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

发明人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

IPC分类号： G06F7/38

CPC分类号： G06F7/60 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

公开(公告)号：US20130198254A1

公开(公告)日：2013-08-01

申请号：US13801356

申请日：2013-03-13

申请人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

发明人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Carole Dulong ,  Eiichi Kowashi ,  Wolf C. Witt

IPC分类号： G06F17/10

CPC分类号： G06F7/60 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/7817 ,  G06F17/10 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

公开(公告)号：US5859997A

公开(公告)日：1999-01-12

申请号：US699993

申请日：1996-08-20

申请人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Wolf Witt ,  Carole Dulong ,  Eiichi Kowashi

发明人： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Wolf Witt ,  Carole Dulong ,  Eiichi Kowashi

IPC分类号： G06F7/544 ,  G06F9/00

CPC分类号： G06F9/30036 ,  G06F7/5443 ,  G06F2207/3828

摘要： A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least one of the data elements in this third packed data storing the result of performing a multiply-subtract operation on data elements in the first and second packed data.

摘要翻译： 一种用于在处理器中包括用于对压缩数据进行乘法减法操作的指令的方法和装置。 在一个实施例中，处理器耦合到存储器。 存储器中存储有第一打包数据和第二打包数据。 处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。 该第三打包数据中的至少一个数据元素存储对第一和第二打包数据中的数据元素进行乘法运算的结果。