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公开(公告)号：US5907305A
公开(公告)日：1999-05-25
申请号：US977004
申请日：1997-11-24
申请人： Larry W. Epp , Abdur R. Khan , R. Peter Smith , Hugh K. Smith
发明人： Larry W. Epp , Abdur R. Khan , R. Peter Smith , Hugh K. Smith
CPC分类号： H01Q1/248 , H01Q1/38 , H01Q3/46 , H01Q9/0435 , H01Q9/0442 , H01Q9/045 , H01Q9/0457
摘要： An aperture coupled patch splits energy from two different polarization components to different locations to spread heat. In addition, there is no physical electrical connection between the slot, patch and circuitry. The circuitry is located under a ground plane which shields against harmonic radiation back to the RF source.
摘要翻译： 孔耦合贴片将能量从两个不同的偏振分量分裂到不同的位置以散热。 此外，插槽，贴片和电路之间没有物理电气连接。 该电路位于接地平面下方，可将谐波辐射屏蔽回RF源。
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公开(公告)号：US09711633B2
公开(公告)日：2017-07-18
申请号：US12118243
申请日：2008-05-09
IPC分类号： H01L21/338 , H01L29/778 , H01L29/08 , H01L29/66 , H01L23/29 , H01L23/31 , H01L29/20
CPC分类号： H01L29/7787 , H01L23/291 , H01L23/3171 , H01L29/0843 , H01L29/2003 , H01L29/66462 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a semiconductor device include forming a dielectric layer on a Group III-nitride semiconductor layer, selectively removing portions of the dielectric layer over spaced apart source and drain regions of the semiconductor layer, implanting ions having a first conductivity type directly into the source and drain regions of the semiconductor layer, annealing the semiconductor layer and the dielectric layer to activate the implanted ions, and forming metal contacts on the source and drain regions of the semiconductor layer.
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3.发明申请SEMICONDUCTOR DEVICES INCLUDING SHALLOW IMPLANTED REGIONS AND METHODS OF FORMING THE SAME 有权包括浅层植入区域的半导体器件及其形成方法公开(公告)号：US20110057232A1
公开(公告)日：2011-03-10
申请号：US12118243
申请日：2008-05-09
IPC分类号： H01L29/737 , H01L21/338
CPC分类号： H01L29/7787 , H01L23/291 , H01L23/3171 , H01L29/0843 , H01L29/2003 , H01L29/66462 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a semiconductor device include forming a dielectric layer on a Group III-nitride semiconductor layer, selectively removing portions of the dielectric layer over spaced apart source and drain regions of the semiconductor layer, implanting ions having a first conductivity type directly into the source and drain regions of the semiconductor layer, annealing the semiconductor layer and the dielectric layer to activate the implanted ions, and forming metal contacts on the source and drain regions of the semiconductor layer.
摘要翻译： 形成半导体器件的方法包括在III族氮化物半导体层上形成电介质层，在半导体层的间隔开的源极和漏极区域上选择性地去除电介质层的部分，将具有第一导电类型的离子直接注入到源 和漏区，退火半导体层和电介质层以激活注入的离子，并在半导体层的源极和漏极区上形成金属接触。
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4.发明授权Methods of fabricating transistors including self-aligned gate electrodes and source/drain regions 有权制造晶体管的方法包括自对准栅电极和源/漏区公开(公告)号：US08105889B2
公开(公告)日：2012-01-31
申请号：US12509855
申请日：2009-07-27
申请人： R. Peter Smith , Scott T. Sheppard
发明人： R. Peter Smith , Scott T. Sheppard
IPC分类号： H01L21/338
CPC分类号： H01L29/2003 , B82Y10/00 , H01L21/26553 , H01L21/28587 , H01L29/15 , H01L29/402 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/66871 , H01L29/66878 , H01L29/7787 , H01L29/812
摘要： Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.
摘要翻译： 形成III族氮化物晶体管器件的方法包括在III族氮化物半导体层上形成保护层，在保护层上形成通孔以暴露出III族氮化物半导体层的一部分，并形成掩模栅极 保护层。 掩模门包括具有比通孔宽度大的宽度的上部，并且具有延伸到通孔中的下部。 所述方法还包括使用掩模栅极作为植入掩模将源极/漏极区域注入到III族氮化物半导体层中。
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5.发明申请METHODS OF FABRICATING TRANSISTORS INCLUDING SELF-ALIGNED GATE ELECTRODES AND SOURCE/DRAIN REGIONS 有权制造晶体管的方法，包括自对准的栅极电极和源/漏区公开(公告)号：US20110018040A1
公开(公告)日：2011-01-27
申请号：US12509855
申请日：2009-07-27
申请人： R. Peter Smith , Scott T. Sheppard
发明人： R. Peter Smith , Scott T. Sheppard
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/2003 , B82Y10/00 , H01L21/26553 , H01L21/28587 , H01L29/15 , H01L29/402 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/66871 , H01L29/66878 , H01L29/7787 , H01L29/812
摘要： Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.
摘要翻译： 形成III族氮化物晶体管器件的方法包括在III族氮化物半导体层上形成保护层，在保护层上形成通孔以暴露出III族氮化物半导体层的一部分，并形成掩模栅极 保护层。 掩模门包括具有比通孔宽度大的宽度的上部，并且具有延伸到通孔中的下部。 所述方法还包括使用掩模栅极作为植入掩模将源极/漏极区域注入到III族氮化物半导体层中。
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