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1.发明授权System and method for providing a clock and data recovery circuit with a fast bit error rate self test capability 有权提供具有快速误码率自检能力的时钟和数据恢复电路的系统和方法公开(公告)号：US07571360B1
公开(公告)日：2009-08-04
申请号：US10973843
申请日：2004-10-26
IPC分类号： G06F11/00
CPC分类号： G06F11/2215
摘要： A system and method is disclosed for providing a clock and data recovery circuit with a fast bit error rate self test capability. A bit error rate test control unit is provided that causes the clock and data recovery circuit to sample data adjacent to an edge of a bit period to create errors at a relatively high bit error rate. This is accomplished by intentionally introducing an interpolator offset in a phase position of a data clock signal. The test control unit generates a first bit error rate and then subsequently generates a second bit error rate. The test control unit then uses the values of the first and second bit error rates to extrapolate a value of bit error rate for the clock and data recovery circuit that corresponds to a zero value of interpolator offset.
摘要翻译： 公开了一种提供具有快速误码率自检能力的时钟和数据恢复电路的系统和方法。 提供了一个误码率测试控制单元，使得时钟和数据恢复电路对位周期边缘附近的数据采样，以相对较高的误码率产生错误。 这是通过有意地在数据时钟信号的相位位置引入内插器偏移来实现的。 测试控制单元产生第一误码率，然后产生第二误码率。 测试控制单元然后使用第一和第二位错误率的值来推断对应于内插器偏移的零值的时钟和数据恢复电路的误码率值。
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2.发明授权System and method for providing a clock and data recovery circuit with a self test capability 有权提供具有自检功能的时钟和数据恢复电路的系统和方法公开(公告)号：US07555091B1
公开(公告)日：2009-06-30
申请号：US10973131
申请日：2004-10-26
IPC分类号： H03D3/24
CPC分类号： H04L7/0079 , G01R31/31715 , G01R31/31726 , H03L7/0814 , H03L7/087 , H03L7/091 , H04L1/24 , H04L7/0025 , H04L7/033
摘要： A system and method is disclosed for providing a clock and data recovery circuit with a self test capability. A test control unit is provided that causes the clock and data recovery circuit to continuously alter a phase of an interpolated clock signal. A user selects a preselected bit pattern that causes the digital control circuitry of the clock and data recovery circuit to advance or retard the phase of the interpolated clock signal. The test control unit compares the advanced or retarded phase of the interpolated clock signal with a reference clock signal to determine a frequency difference between the two clock signals. The test control unit uses the frequency difference to determine the test status of the clock and data recovery circuit.
摘要翻译： 公开了一种用于提供具有自检能力的时钟和数据恢复电路的系统和方法。 提供了一种使时钟和数据恢复电路连续地改变内插时钟信号的相位的测试控制单元。 用户选择使得时钟和数据恢复电路的数字控制电路推进或延迟内插时钟信号的相位的预选位模式。 测试控制单元将内插时钟信号的高级或延迟相位与参考时钟信号进行比较，以确定两个时钟信号之间的频率差。 测试控制单元使用频率差来确定时钟和数据恢复电路的测试状态。
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3.发明授权System and method for providing a low jitter data receiver for serial links with a regulated single ended phase interpolator 有权用于提供用于与调节单端相位内插器的串行链路的低抖动数据接收器的系统和方法公开(公告)号：US07233173B1
公开(公告)日：2007-06-19
申请号：US10973743
申请日：2004-10-26
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/02 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/222 , H03K3/356034 , H03K3/356086 , H03K5/003 , H03K5/082
摘要： A system and method is disclosed for providing a clock and data recovery circuit that comprises a low jitter data receiver. The low jitter data receiver comprises a phase interpolator, an amplifier unit and a data sampling comparator. The phase interpolator and the amplifier unit provide the data sampling comparator with a single ended clock signal that is relatively immune to power supply noise. The data sampling comparator samples an input data stream with minimal jitter due to power supply noise. The data sampling comparator consumes less static power than a current mode logic D flip flop and also has output levels that are compatible with complementary metal oxide semiconductor (CMOS) logic.
摘要翻译： 公开了一种用于提供包括低抖动数据接收器的时钟和数据恢复电路的系统和方法。 低抖动数据接收机包括相位内插器，放大器单元和数据采样比较器。 相位内插器和放大器单元为数据采样比较器提供相对免受电源噪声的单端时钟信号。 数据采样比较器由于电源噪声而以最小的抖动对输入数据流进行采样。 数据采样比较器消耗的静态功耗比电流模式逻辑D触发器少，并且还具有与互补金属氧化物半导体（CMOS）逻辑兼容的输出电平。
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公开(公告)号：US08588289B2
公开(公告)日：2013-11-19
申请号：US13183932
申请日：2011-07-15
IPC分类号： H03H7/40
CPC分类号： H04L25/03885 , H04B3/00 , H04L25/00
摘要： Circuitry for adaptive signal equalizing with coarse and fine boost controls by providing multiple serially coupled stages of parallel controllable DC and AC signal gains with coarse and fine gain controls provided across all stages.
摘要翻译： 通过提供并联可控直流和交流信号增益的多个串联耦合级，提供了跨越所有阶段的粗略和精细增益控制，用于自适应信号均衡的粗略和精细升压控制电路。
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公开(公告)号：US20120188014A1
公开(公告)日：2012-07-26
申请号：US13183932
申请日：2011-07-15
IPC分类号： H03F3/45
CPC分类号： H04L25/03885 , H04B3/00 , H04L25/00
摘要： Circuitry for adaptive signal equalizing with coarse and fine boost controls by providing multiple serially coupled stages of parallel controllable DC and AC signal gains with coarse and fine gain controls provided across all stages.
摘要翻译： 通过提供并联可控直流和交流信号增益的多个串联耦合级，提供了跨越所有阶段的粗略和精细增益控制，用于自适应信号均衡的粗略和精细升压控制电路。
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6.发明授权System and method for providing a parameterized analog feedback loop for continuous time adaptive equalization incorporating low frequency attenuation gain compensation 有权用于提供用于连续时间自适应均衡的参数化模拟反馈回路的系统和方法，其包括低频衰减增益补偿公开(公告)号：US07778323B1
公开(公告)日：2010-08-17
申请号：US11044988
申请日：2005-01-27
IPC分类号： H03H7/30
CPC分类号： H04L25/03038
摘要： A system and a method are disclosed for providing a parameterized analog feedback loop for continuous time adaptive equalization that incorporates low frequency attenuation gain compensation. N adaptive equalizer stages are coupled in series and a slicer circuit is coupled to the last (Nth) adaptive equalizer stage. A single equalizer adaptation control loop controls the frequency response of the adaptive equalizer stages to compensate for the attenuation of a lossy channel. The single equalizer adaptation control loop also compensates for the direct current (DC) loss in the lossy channel by modulating a bias current in the slicer circuit to scale the low frequency feedback with adaptation coefficients that correlate with channel length.
摘要翻译： 公开了一种系统和方法，用于提供用于连续时间自适应均衡的参数化模拟反馈环路，其包括低频衰减增益补偿。 N个自适应均衡器级串联耦合，并且限幅电路耦合到最后（第N个）自适应均衡器级。 单个均衡器适配控制环路控制自适应均衡器级的频率响应以补偿有损信道的衰减。 单个均衡器自适应控制环路还通过调制限幅器电路中的偏置电流来补偿有损信道中的直流（DC）损耗，以便通过与信道长度相关的适配系数来缩放低频反馈。
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7.发明授权Device and computer system for power management using serial link connections 有权使用串行链路连接进行电源管理的设备和计算机系统公开(公告)号：US07404090B1
公开(公告)日：2008-07-22
申请号：US10966885
申请日：2004-10-15
申请人： Laurence Lewicki , Nicolas Nodenot
发明人： Laurence Lewicki , Nicolas Nodenot
CPC分类号： G06F1/324 , G06F1/3215 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Power management for a computer system and device is accomplished by implementing two separate power modes in a serially-connected device, and selecting from the two power modes depending on the state of a receiver in the device. A signal detector within the receiver is connected to a serial interface port of the device to detect the presence of an input signal. A power controller selects a first power mode for the device when the signal detector detects the input signal and a second power mode for the device when the input signal is not detected by the signal detector.
摘要翻译： 计算机系统和设备的电源管理通过在串行连接的设备中实现两个独立的功率模式来实现，并且根据设备中的接收器的状态从两种功率模式中进行选择。 接收机内的信号检测器连接到设备的串行接口端口，以检测输入信号的存在。 当信号检测器检测到输入信号时，功率控制器选择设备的第一功率模式，并且当信号检测器未检测到输入信号时，功率控制器选择用于器件的第二功率模式。
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8.发明授权System and method for adaptively equalizing data signals with higher and lower data rates 有权用于以更高和更低数据速率自适应地均衡数据信号的系统和方法公开(公告)号：US08270463B1
公开(公告)日：2012-09-18
申请号：US13228249
申请日：2011-09-08
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04B3/00 , H04L25/00
摘要： System and method for adaptive signal equalizing in which overlapping data signal equalization paths provide cumulative data signal equalization to provide multiple equalized data signals having different available amounts of equalization. Signal slicing circuitry slices the equalized data signals to provide multiple sliced data signals, from which the sliced data signal selected as an output data signal is dependent upon the data rate of the incoming data signal.
摘要翻译： 用于自适应信号均衡的系统和方法，其中重叠数据信号均衡路径提供累积数据信号均衡以提供具有不同可用量均衡的多个均衡数据信号。 信号分片电路对均衡的数据信号进行切片以提供多个分片数据信号，从中选择作为输出数据信号的分片数据信号取决于输入数据信号的数据速率。
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9.发明授权System and method for providing adaptively equalized data signal with alternately adjusted data signal boost and sliced data signal amplitude 有权用于提供具有交替调整的数据信号升压和分片数据信号幅度的自适应均衡数据信号的系统和方法公开(公告)号：US08325791B1
公开(公告)日：2012-12-04
申请号：US13228217
申请日：2011-09-08
IPC分类号： H04B3/46
CPC分类号： H04L25/03885 , H04B3/00 , H04L25/00
摘要： Method and system for adaptive signal equalizing with alternating boost and amplitude controls. In accordance with one exemplary embodiment, data signal boost control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a higher frequency, while sliced data signal amplitude control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a lower frequency.
摘要翻译： 用于交替升压和幅度控制的自适应信号均衡的方法和系统。 根据一个示例性实施例，数据信号升高控制基于在围绕更高频率设置的带宽内的测量的均衡和分片的数据信号能量，而分片数据信号幅度控制基于在所布置的带宽内的测量的均衡和分片的数据信号能量 关于较低的频率。
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