公开(公告)号：US20090117360A1

公开(公告)日：2009-05-07

申请号：US11933760

申请日：2007-11-01

申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Habib Hichri ,  Louis L. Hsu ,  Kaushik A. Kumar ,  Carl Radens ,  Shahab Siddiqui ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Habib Hichri ,  Louis L. Hsu ,  Kaushik A. Kumar ,  Carl Radens ,  Shahab Siddiqui ,  Chih-Chao Yang

IPC分类号： G03C1/73 ,  B05D3/00 ,  B32B27/06

CPC分类号： H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y30/00 ,  H01L21/0338

摘要： A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features of nanometer scale, including at least one recessed region having a nanoscale dimension is formed in the polymeric resist. The top surface of the polymeric resist is modified for enhanced etch resistance by an exposure to an energetic beam, which allows the top surface of the patterned polymeric resist to become more resistant to etching processes and chemistries. The enhanced ratio of etch resistance between the two types of surfaces provides improved image contrast and fidelity between areas having the top surface and the at least one recessed region.

摘要翻译： 含有至少两个不混溶的聚合物嵌段组分的非光敏聚合物抗蚀剂沉积在平面上。 将非光敏聚合物抗蚀剂退火以允许不相容组分的相分离并显影以除去至少两种聚合物嵌段组分中的至少一种。 在聚合物抗蚀剂中形成纳米尺度特征，即纳米尺度的特征，包括具有纳米级尺寸的至少一个凹陷区域。 聚合物抗蚀剂的顶表面通过暴露于能量束而被改进以提高耐蚀刻性，这允许图案化聚合物抗蚀剂的顶表面变得更耐蚀刻工艺和化学物质。 两种类型表面之间的增强的耐蚀刻比提供了改善的图像对比度和具有顶表面和至少一个凹陷区域的区域之间的保真度。

公开(公告)号：US07494915B2

公开(公告)日：2009-02-24

申请号：US11463447

申请日：2006-08-09

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

公开(公告)号：US07122462B2

公开(公告)日：2006-10-17

申请号：US10707122

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

公开(公告)号：US07001835B2

公开(公告)日：2006-02-21

申请号：US10707119

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

IPC分类号： H01L21/4763

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/76841 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.

摘要翻译： 集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和 通过硬掩模和ILD的中间层降低对准标记。 形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

公开(公告)号：US07648871B2

公开(公告)日：2010-01-19

申请号：US11163523

申请日：2005-10-21

申请人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Kaushik A. Kumar ,  Carl Radens

发明人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Kaushik A. Kumar ,  Carl Radens

IPC分类号： H01L21/8238

CPC分类号： H01L21/76804 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.

摘要翻译： 本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。 倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。 优选地，反相源极/漏极金属触点的下部具有约0.03mum2至约3.15mum2的横截面积，并且这种反向的源极/漏极金属触点与FET的栅电极间隔开一个 距离范围从约0.001毫米到约5毫米。

公开(公告)号：US07659160B2

公开(公告)日：2010-02-09

申请号：US11923075

申请日：2007-10-24

申请人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Kaushik A. Kumar ,  Carl Radens

发明人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Lawrence A. Clevenger ,  Kaushik A. Kumar ,  Carl Radens

IPC分类号： H01L21/8238

CPC分类号： H01L21/76804 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.

摘要翻译： 本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。 倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。 优选地，反相源极/漏极金属触点的下部具有约0.03mum2至约3.15mum2的横截面积，并且这种反向的源极/漏极金属触点与FET的栅电极间隔开一个 距离范围从约0.001毫米到约5毫米。

公开(公告)号：US08030157B1

公开(公告)日：2011-10-04

申请号：US12782050

申请日：2010-05-18

申请人： Habib Hichri ,  Ahmad D. Katnani ,  Kaushik A. Kumar ,  Narender Rana ,  Richard S. Wise ,  Hakeem B. S. Akinmade-Yusuff

发明人： Habib Hichri ,  Ahmad D. Katnani ,  Kaushik A. Kumar ,  Narender Rana ,  Richard S. Wise ,  Hakeem B. S. Akinmade-Yusuff

IPC分类号： H01L21/8242

CPC分类号： H01L21/76232

摘要： A method of forming a trench in a semiconductor device formed of a substrate and a first layer formed over the substrate includes forming an initial trench that passes through the first layer to the substrate, the initial trench having a diameter that decreases from a first diameter to a second diameter, the second diameter being measured at a distance closer to the substrate than the first diameter; exposing the trench to a dopant via an orthogonal ion implant to form doped regions sidewalls of the trench; and etching the trench to remove at least some of the doped regions.

摘要翻译： 在由衬底和形成在衬底上的第一层形成的半导体器件中形成沟槽的方法包括形成通过第一层到衬底的初始沟槽，初始沟槽的直径从第一直径减小到 第二直径，第二直径在比第一直径更靠近基板的距离处被测量; 通过正交离子注入将沟槽暴露于掺杂剂以形成沟槽的掺杂区域侧壁; 并蚀刻沟槽以去除至少一些掺杂区域。

公开(公告)号：US07851919B2

公开(公告)日：2010-12-14

申请号：US12701045

申请日：2010-02-05

申请人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L21/40

CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

摘要翻译： 公开了包括金属互连的金属互连和IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质更低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。

公开(公告)号：US20100133694A1

公开(公告)日：2010-06-03

申请号：US12701045

申请日：2010-02-05

申请人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L23/48 ,  H01L23/498

CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

摘要翻译： 公开了包括金属互连的金属互连和IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。

公开(公告)号：US07718525B2

公开(公告)日：2010-05-18

申请号：US11770928

申请日：2007-06-29

申请人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

摘要翻译： 公开了形成金属互连的方法和包括金属互连的IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质更低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。