公开(公告)号：US07001835B2

公开(公告)日：2006-02-21

申请号：US10707119

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

IPC分类号： H01L21/4763

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/76841 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.

摘要翻译： 集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和 通过硬掩模和ILD的中间层降低对准标记。 形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

公开(公告)号：US07494915B2

公开(公告)日：2009-02-24

申请号：US11463447

申请日：2006-08-09

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

公开(公告)号：US07122462B2

公开(公告)日：2006-10-17

申请号：US10707122

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

公开(公告)号：US07064064B2

公开(公告)日：2006-06-20

申请号：US11058783

申请日：2005-02-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US07563710B2

公开(公告)日：2009-07-21

申请号：US11860602

申请日：2007-09-25

申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a damascene wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor.

摘要翻译： 一种形成镶嵌线的方法。 该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。

公开(公告)号：US06975032B2

公开(公告)日：2005-12-13

申请号：US10319967

申请日：2002-12-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

公开(公告)号：US20080246151A1

公开(公告)日：2008-10-09

申请号：US12140352

申请日：2008-06-17

申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

IPC分类号： H01L23/52

CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

公开(公告)号：US07598616B2

公开(公告)日：2009-10-06

申请号：US12140352

申请日：2008-06-17

申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

IPC分类号： H01L29/06 ,  H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure. The structure includes: a core electrical conductor having a top surface, an opposite bottom surface and sides between the top and bottom surfaces; an electrically conductive liner in direct physical contact with and covering the bottom surface and the sides of the core electrical conductor, embedded portions of the electrically conductive liner in direct physical contact with and extending over the core electrical conductor in regions of the core electrical conductor adjacent to both the top surface and the sides of the core electrical conductor; and an electrically conductive cap in direct physical contact with the top surface of the core electrical conductor that is exposed between the embedded portions of the electrically conductive liner.

摘要翻译： 一个结构。 该结构包括：具有顶表面，相对的底表面和顶表面和底表面之间的侧面的芯电导体; 与芯电导体的底表面和侧面直接物理接触并覆盖芯电导体的底表面和侧面的导电衬垫，导电衬垫的嵌入部分与芯电导体相邻的芯电导体的区域中直接物理接触并延伸 到芯电导体的顶表面和侧面; 以及与导电衬里的嵌入部分之间暴露的芯电导体的顶表面直接物理接触的导电帽。

公开(公告)号：US07528493B2

公开(公告)日：2009-05-05

申请号：US11860590

申请日：2007-09-25

申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

IPC分类号： H01L29/06 ,  H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

摘要翻译： 一种镶嵌线及其形成方法。 该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。 该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。

公开(公告)号：US07335588B2

公开(公告)日：2008-02-26

申请号：US11107074

申请日：2005-04-15

申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

IPC分类号： H01L24/4763

CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

摘要翻译： 一种镶嵌线及其形成方法。 该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。 该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。