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    Transceiver having multiple signal processing modes of operation
    4.
    发明申请
    Transceiver having multiple signal processing modes of operation 有权
    收发器具有多种信号处理操作模式

    公开(公告)号：US20080049817A1

    公开(公告)日：2008-02-28

    申请号：US11824568

    申请日：2007-06-29

    申请人： Lawrence Der ,  George Tuttle ,  Alessandro Piovaccari ,  Chunyu Xin ,  Scott Haban ,  Javier Elenes ,  Dan Kasha ,  Peter Vancorenland

    发明人： Lawrence Der ,  George Tuttle ,  Alessandro Piovaccari ,  Chunyu Xin ,  Scott Haban ,  Javier Elenes ,  Dan Kasha ,  Peter Vancorenland

    IPC分类号： H04B1/38

    CPC分类号： H04B1/40 ,  H03M3/398 ,  H03M3/40 ,  H03M3/448 ,  H03M3/452 ,  H03M3/50

    摘要： A transceiver includes a processor, which is adapted to in a transmit mode of the transceiver, form at least part of a transmitter and in a receive mode of the transceiver, form at least part of a receiver. The transceiver may include at least one analog-to-digital converter to provide digital signals to the processor in both the transmit and receive modes of operation; and the transceiver may include at least one digital-to-analog converter to receive digital signals from the processor in the transmit and receive modes of operation. The processor may be fabricated on an integrated circuit with at least one of the analog-to-digital converters and/or with at least one of the digital-to-analog converters.

    摘要翻译： 收发器包括适于处于收发器的发射模式的处理器，形成发射器的至少一部分并且在收发器的接收模式中形成接收器的至少一部分。 收发器可以包括至少一个模拟 - 数字转换器，以在发送和接收操作模式中向处理器提供数字信号; 并且收发器可以包括至少一个数模转换器，以在发送和接收操作模式中从处理器接收数字信号。 处理器可以在与至少一个模数转换器和/或至少一个数模转换器的集成电路上制造。

    Computational method, system, and apparatus
    5.
    发明授权
    Computational method, system, and apparatus 有权
    计算方法，系统和装置

    公开(公告)号：US08024392B2

    公开(公告)日：2011-09-20

    申请号：US11801333

    申请日：2007-05-09

    申请人： Greg North ,  Scott Haban ,  Kyle Stein

    发明人： Greg North ,  Scott Haban ,  Kyle Stein

    IPC分类号： G06F7/38

    CPC分类号： G06F7/72 ,  G01N2035/00247 ,  G01N2035/00574 ,  G06F7/723 ,  G06F7/727 ,  G06F7/728 ,  G11C7/1066

    摘要： A method, system, and apparatus for performing computations.In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, XP and XQ. XP and XQ are exponentiated to compute, respectively, CP and CQ. CP and CQ are merged to compute C, which is then retrieved from the session memory.A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations.An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.

    摘要翻译： 一种用于执行计算的方法，系统和装置。 在一种方法中，将参数X和K加载到会话存储器中，并且计算X mod P和X mod Q以分别给出XP和XQ。 XP和XQ分别乘以CP和CQ进行计算。 CP和CQ合并为计算C，然后从会话存储器检索。 一种系统包括计算设备和至少一个计算设备，其中所述计算设备被配置为使用所述计算设备来执行加速计算。 一种装置包括链接控制器和多个计算装置。 多个计算设备的第一链接子集包括多个计算设备中的至少两个，并且链接控制器被配置为指示第一链接子集作为第一计算链进行操作。

    Controlling passthrough of communication between multiple buses
    6.
    发明授权
    Controlling passthrough of communication between multiple buses 有权
    控制多台总线之间通信的通路

    公开(公告)号：US08151029B2

    公开(公告)日：2012-04-03

    申请号：US12981769

    申请日：2010-12-30

    申请人： Scott Haban ,  Dylan Hester ,  Ruifeng Sun

    发明人： Scott Haban ,  Dylan Hester ,  Ruifeng Sun

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4282

    摘要： A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

    摘要翻译： 解调器可以包括经由第一总线将解调器耦合到主机设备的第一数据和时钟焊盘，以及经由第二总线将解调器耦合到射频（RF）调谐器的第二数据和时钟焊盘。 该设备还可以包括用于将主机数据和主机时钟从第一总线耦合到第二总线的通过逻辑，并且在直通模式期间将调谐器数据从第二总线耦合到第一总线。 然而，在这种模式下，两条总线可能保持电气分离。 当禁用直通模式时，RF调谐器被屏蔽，避免了第一个总线上存在的噪声。

    CONTROLLING PASSTHROUGH OF COMMUNICATION BETWEEN MULTIPLE BUSES
    7.
    发明申请
    CONTROLLING PASSTHROUGH OF COMMUNICATION BETWEEN MULTIPLE BUSES 有权
    控制多个通讯之间的通信

    公开(公告)号：US20110099310A1

    公开(公告)日：2011-04-28

    申请号：US12981769

    申请日：2010-12-30

    申请人： Scott Haban ,  Dylan Hester ,  Ruifeng Sun

    发明人： Scott Haban ,  Dylan Hester ,  Ruifeng Sun

    IPC分类号： G06F13/36 ,  G06F13/00

    CPC分类号： G06F13/4282

    摘要： A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

    摘要翻译： 解调器可以包括经由第一总线将解调器耦合到主机设备的第一数据和时钟焊盘，以及经由第二总线将解调器耦合到射频（RF）调谐器的第二数据和时钟焊盘。 该设备还可以包括用于将主机数据和主机时钟从第一总线耦合到第二总线的通过逻辑，并且在直通模式期间将调谐器数据从第二总线耦合到第一总线。 然而，在这种模式下，两条总线可能保持电气分离。 当禁用直通模式时，RF调谐器被屏蔽，避免了第一个总线上存在的噪声。

    Digital Architecture Using One-Time Programmable (OTP) Memory
    8.
    发明申请
    Digital Architecture Using One-Time Programmable (OTP) Memory 有权
    使用一次性可编程（OTP）存储器的数字架构

    公开(公告)号：US20100009640A1

    公开(公告)日：2010-01-14

    申请号：US12562357

    申请日：2009-09-18

    申请人： Scott Haban ,  G. Tyson Tuttle ,  Gregory A. Hodgson

    发明人： Scott Haban ,  G. Tyson Tuttle ,  Gregory A. Hodgson

    IPC分类号： H04B1/40 ,  G06F12/02 ,  G06F15/76 ,  G06F9/06

    CPC分类号： G06F8/60

    摘要： In one aspect, the present invention includes an apparatus having a digital signal processor (DSP), a controller coupled to the DSP to provide control signals to the DSP, and a one-time programmable (OTP) memory coupled to the DSP and the controller. The OTP memory may include multiple code portions including a first code block to control the DSP and a second code block to control the controller.

    摘要翻译： 一方面，本发明包括具有数字信号处理器（DSP）的装置，耦合到DSP以向DSP提供控制信号的控制器以及耦合到DSP和控制器的一次可编程（OTP）存储器 。 OTP存储器可以包括多个代码部分，包括用于控制DSP的第一代码块和用于控制控制器的第二代码块。

    Clock generator circuitry
    9.
    发明授权
    Clock generator circuitry 有权
    时钟发生器电路

    公开(公告)号：US06779125B1

    公开(公告)日：2004-08-17

    申请号：US09590596

    申请日：2000-06-09

    申请人： Scott Haban

    发明人： Scott Haban

    IPC分类号： G06F104

    CPC分类号： H03K3/356113 ,  H03K3/356182

    摘要： Clock generation circuitry 1300 includes an oscillator 1302 for generating a first signal from a crystal 1301 of a selected oscillating frequency. A first frequency multiplier 1304 selectively multiplies the frequency of the first signal by a predetermined factor to obtain a second signal having a frequency of a preselected multiple of a first set of clock signals. A divider 1305 selectively divides the frequency of the second signal by a second factor to obtain a third signal of a selected frequency. A second frequency multiplier 1304 selectively multiplies the frequency of the third signal by a third factor to obtain a fourth signal of a selected frequency, the second and third factors selected to produce a fourth signal having a frequency of a preselected multiple of a second set of

    摘要翻译： 时钟产生电路1300包括用于从所选振荡频率的晶体1301产生第一信号的振荡器1302。 第一倍频器1304选择性地将第一信号的频率乘以预定因子以获得具有第一组时钟信号的预选倍数的频率的第二信号。 分频器1305选择性地将第二信号的频率除以第二因子以获得选定频率的第三信号。 第二倍频器1304选择性地将第三信号的频率乘以第三因子以获得所选频率的第四信号，所选择的第二和第三因素产生第四信号，该第四信号具有第二组的预选倍数