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公开(公告)号:US07498665B2
公开(公告)日:2009-03-03
申请号:US11381726
申请日:2006-05-04
IPC分类号: H01L23/495 , H01L21/44
CPC分类号: H01L23/3107 , H01L23/49541 , H01L24/97 , H01L2224/48247 , H01L2224/49171 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要: An integrated circuit leadless package system is presented comprising forming a QFN leadframe comprises providing a die pad, forming a fishtail tie-bar on the die pad, forming a row of an outer contact pad around the die pad, forming an additional outer contact pad around the fishtail tie-bar, and forming an inner contact pad in a staggered position from the outer contact pad, mounting an integrated circuit on the die pad of the QFN leadframe, and attaching a bond wire from the integrated circuit to the additional outer contact pad.
摘要翻译: 提供了一种集成电路无引线封装系统,包括形成QFN引线框架,包括提供管芯焊盘,在管芯焊盘上形成鱼尾连接杆,在管芯焊盘周围形成一排外部接触焊盘,形成附近的外部接触焊盘 钓鱼连接杆,并且从外部接触垫形成交错位置的内部接触垫,将集成电路安装在QFN引线框架的管芯焊盘上,以及将来自集成电路的接合线附接到附加的外部接触焊盘 。
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公开(公告)号:US07598598B1
公开(公告)日:2009-10-06
申请号:US10910089
申请日:2004-08-03
IPC分类号: H01L23/495
CPC分类号: H01L21/4821 , H01L23/3107 , H01L23/49548 , H01L24/48 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/97 , H01L2924/00014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor package comprising a leadframe. The leadframe itself comprises an outer frame portion which defines a central opening. Disposed within the central opening is a die pad which defines opposed, generally planar top and bottom die pad surfaces and a peripheral edge. Connected to and extending between the outer frame portion and the peripheral edge of the die pad is at least one tie bar of the leadframe. The leadframe also includes a plurality of leads which are connected to the outer frame portion and extend into the opening at least partially about the die pad in spaced relation to the peripheral edge thereof. Each of the leads includes opposed, generally planar top and bottom lead surfaces, with at least two of the leads comprising corner leads which extend along opposed sides of the tie bar. Each of the corner leads further defines an angularly offset distal portion which extends along and in spaced relation to the tie bar.
摘要翻译: 一种包括引线框的半导体封装。 引线框本身包括限定中心开口的外框部分。 设置在中心开口内的是一个芯片焊盘,该焊盘限定了相对的,大致平坦的顶部和底部焊盘表面以及外围边缘。 连接到外框架部分和芯片垫的周边边缘之间并且延伸的至少一个引线框架的连接杆。 引线框架还包括多个引线,其连接到外部框架部分并且至少部分地围绕芯片焊盘延伸到与其外围边缘间隔开的开口中。 每个引线包括相对的,大致平坦的顶部和底部引线表面,其中至少两个引线包括沿着连接条的相对侧延伸的角引线。 每个拐角引线还限定了一个沿连接杆延伸并且与连杆间隔开的角度偏移的远端部分。
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公开(公告)号:US06847099B1
公开(公告)日:2005-01-25
申请号:US10358621
申请日:2003-02-05
IPC分类号: H01L21/48 , H01L23/31 , H01L23/495
CPC分类号: H01L21/4821 , H01L23/3107 , H01L23/49548 , H01L24/48 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/97 , H01L2924/00014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor package comprising a leadframe. The leadframe itself comprises an outer frame portion which defines a central opening. Disposed within the central opening is a die pad which defines opposed, generally planar top and bottom die pad surfaces and a peripheral edge. Connected to and extending between the outer frame portion and the peripheral edge of the die pad is at least one tie bar of the leadframe. The leadframe also includes a plurality of leads which are connected to the outer frame portion and extend into the opening at least partially about the die pad in spaced relation to the peripheral edge thereof. Each of the leads includes opposed, generally planar top and bottom lead surfaces, with at least two of the leads comprising corner leads which extend along opposed sides of the tie bar. Each of the corner leads further defines an angularly offset distal portion which extends along and in spaced relation to the tie bar.
摘要翻译: 一种包括引线框的半导体封装。 引线框本身包括限定中心开口的外框部分。 设置在中心开口内的是一个芯片焊盘,该焊盘限定了相对的,大致平坦的顶部和底部焊盘表面以及外围边缘。 连接到外框架部分和芯片垫的周边边缘之间并且延伸的至少一个引线框架的连接杆。 引线框架还包括多个引线,其连接到外部框架部分并且至少部分地围绕芯片焊盘延伸到与其外围边缘间隔开的开口中。 每个引线包括相对的,大致平坦的顶部和底部引线表面,其中至少两个引线包括沿着连接条的相对侧延伸的角引线。 每个拐角引线还限定了一个沿连接杆延伸并且与连杆间隔开的角度偏移的远端部分。
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4.
公开(公告)号:US20090008768A1
公开(公告)日:2009-01-08
申请号:US11773951
申请日:2007-07-05
申请人: Leocadio M. Alabin , Librado Gatbonton , Chiu Hsieh Ong , Beng Yee Teh , Antonio B. Dimaano, JR.
发明人: Leocadio M. Alabin , Librado Gatbonton , Chiu Hsieh Ong , Beng Yee Teh , Antonio B. Dimaano, JR.
IPC分类号: H01L23/48
CPC分类号: H01L24/83 , H01L23/3735 , H01L23/49838 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/2919 , H01L2224/32057 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83385 , H01L2224/8385 , H01L2924/00014 , H01L2924/01015 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor package system including: providing a substrate having a thermal relief thereon; depositing a mask on the substrate and the thermal relief, the mask deposited on the thermal relief and having a regular pattern to partially cover the thermal relief; and die attaching a semiconductor die over the thermal relief.
摘要翻译: 一种半导体封装系统,包括:提供其上具有热释放的衬底; 将掩模沉积在基底和热释放物上,掩模沉积在热浮雕上并具有规则图案以部分地覆盖热释放; 并将半导体管芯贴在热浮雕上。
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公开(公告)号:US07008825B1
公开(公告)日:2006-03-07
申请号:US10445754
申请日:2003-05-27
IPC分类号: G01R31/26 , H01L21/44 , H01L23/495
CPC分类号: G01R31/2896 , H01L21/561 , H01L23/3107 , H01L23/49541 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/05553 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/19105 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A method of fabricating a semiconductor package comprising the step of providing a leadframe strip which defines a strip plane and a multiplicity of leadframes. Each of the leadframes includes an outer frame defining a central opening and a die pad disposed within the central opening. Each leadframe further includes a plurality of leads which are attached to the outer frame and extend toward the die pad in spaced relation to each other. The outer frames are integrally connected to each other and collectively define connecting bars which extend in multiple rows and columns and define saw streets. Semiconductor dies are attached to respective ones of the die pads, with the semiconductor dies being mechanically and electrically connected to the leads of respective ones of the leadframes. Thereafter, an encapsulant material is applied to the leadframe strip to form at least one mold cap which at least partially encapsulates the leadframes, the semiconductor dies, and the conductive wires. The leadframe strip and the mold cap collectively define a package strip. Isolation cuts are formed through the package strip along at least some of the saw streets to effectively electrically isolate the leadframes from each other.
摘要翻译: 一种制造半导体封装的方法,包括提供限定条状平面的引线框条和多个引线框的步骤。 每个引线框架包括限定中心开口的外框架和设置在中央开口内的芯片焊盘。 每个引线框架还包括多个引线,其连接到外框架并且相对于彼此间隔开地朝向管芯焊盘延伸。 外框架彼此一体地连接并且共同地限定连接杆,所述连接杆以多行和列延伸并且限定锯形街道。 半导体管芯附接到相应的管芯焊盘,其中半导体管芯机械地和电连接到引线框架的引线。 此后,将密封剂材料施加到引线框条以形成至少一个至少部分地封装引线框,半导体管芯和导线的模具盖。 引线框条和模盖共同限定了封装条。 隔离切口通过沿着至少一些锯道的包装带形成,以有效地将引线框彼此电隔离。
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6.
公开(公告)号:US08274145B2
公开(公告)日:2012-09-25
申请号:US11773951
申请日:2007-07-05
申请人: Leocadio M. Alabin , Librado Gatbonton , Chiu Hsieh Ong , Beng Yee Teh , Antonio B. Dimaano, Jr.
发明人: Leocadio M. Alabin , Librado Gatbonton , Chiu Hsieh Ong , Beng Yee Teh , Antonio B. Dimaano, Jr.
IPC分类号: H01L23/48
CPC分类号: H01L24/83 , H01L23/3735 , H01L23/49838 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/2919 , H01L2224/32057 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83385 , H01L2224/8385 , H01L2924/00014 , H01L2924/01015 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A semiconductor package system including: providing a substrate having a thermal relief thereon; depositing a mask on the substrate and the thermal relief, the mask deposited on the thermal relief and having a regular pattern to partially cover the thermal relief; and die attaching a semiconductor die over the thermal relief.
摘要翻译: 一种半导体封装系统,包括:提供其上具有热释放的衬底; 将掩模沉积在基底和热释放物上,掩模沉积在热浮雕上并具有规则图案以部分地覆盖热释放; 并将半导体管芯贴在热浮雕上。
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