公开(公告)号：US07598598B1

公开(公告)日：2009-10-06

申请号：US10910089

申请日：2004-08-03

申请人： Ludovico Bancod ,  Gregorio G. Dela Cruz ,  Fidelyn R. Canoy ,  Leocadio M. Alabin

发明人： Ludovico Bancod ,  Gregorio G. Dela Cruz ,  Fidelyn R. Canoy ,  Leocadio M. Alabin

IPC分类号： H01L23/495

CPC分类号： H01L21/4821 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package comprising a leadframe. The leadframe itself comprises an outer frame portion which defines a central opening. Disposed within the central opening is a die pad which defines opposed, generally planar top and bottom die pad surfaces and a peripheral edge. Connected to and extending between the outer frame portion and the peripheral edge of the die pad is at least one tie bar of the leadframe. The leadframe also includes a plurality of leads which are connected to the outer frame portion and extend into the opening at least partially about the die pad in spaced relation to the peripheral edge thereof. Each of the leads includes opposed, generally planar top and bottom lead surfaces, with at least two of the leads comprising corner leads which extend along opposed sides of the tie bar. Each of the corner leads further defines an angularly offset distal portion which extends along and in spaced relation to the tie bar.

摘要翻译： 一种包括引线框的半导体封装。 引线框本身包括限定中心开口的外框部分。 设置在中心开口内的是一个芯片焊盘，该焊盘限定了相对的，大致平坦的顶部和底部焊盘表面以及外围边缘。 连接到外框架部分和芯片垫的周边边缘之间并且延伸的至少一个引线框架的连接杆。 引线框架还包括多个引线，其连接到外部框架部分并且至少部分地围绕芯片焊盘延伸到与其外围边缘间隔开的开口中。 每个引线包括相对的，大致平坦的顶部和底部引线表面，其中至少两个引线包括沿着连接条的相对侧延伸的角引线。 每个拐角引线还限定了一个沿连接杆延伸并且与连杆间隔开的角度偏移的远端部分。

公开(公告)号：US06847099B1

公开(公告)日：2005-01-25

申请号：US10358621

申请日：2003-02-05

申请人： Ludovico Bancod ,  Gregorio G. Dela Cruz ,  Fidelyn R. Canoy ,  Leocadio M. Alabin

发明人： Ludovico Bancod ,  Gregorio G. Dela Cruz ,  Fidelyn R. Canoy ,  Leocadio M. Alabin

IPC分类号： H01L21/48 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L21/4821 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package comprising a leadframe. The leadframe itself comprises an outer frame portion which defines a central opening. Disposed within the central opening is a die pad which defines opposed, generally planar top and bottom die pad surfaces and a peripheral edge. Connected to and extending between the outer frame portion and the peripheral edge of the die pad is at least one tie bar of the leadframe. The leadframe also includes a plurality of leads which are connected to the outer frame portion and extend into the opening at least partially about the die pad in spaced relation to the peripheral edge thereof. Each of the leads includes opposed, generally planar top and bottom lead surfaces, with at least two of the leads comprising corner leads which extend along opposed sides of the tie bar. Each of the corner leads further defines an angularly offset distal portion which extends along and in spaced relation to the tie bar.

摘要翻译： 一种包括引线框的半导体封装。 引线框本身包括限定中心开口的外框部分。 设置在中心开口内的是一个芯片焊盘，该焊盘限定了相对的，大致平坦的顶部和底部焊盘表面以及外围边缘。 连接到外框架部分和芯片垫的周边边缘之间并且延伸的至少一个引线框架的连接杆。 引线框架还包括多个引线，其连接到外部框架部分并且至少部分地围绕芯片焊盘延伸到与其外围边缘间隔开的开口中。 每个引线包括相对的，大致平坦的顶部和底部引线表面，其中至少两个引线包括沿着连接条的相对侧延伸的角引线。 每个拐角引线还限定了一个沿连接杆延伸并且与连杆间隔开的角度偏移的远端部分。

公开(公告)号：US06611047B2

公开(公告)日：2003-08-26

申请号：US09976866

申请日：2001-10-12

申请人： Tom Hu ,  Terry W. Davis ,  Ludovico Bancod

发明人： Tom Hu ,  Terry W. Davis ,  Ludovico Bancod

IPC分类号： H01L23495

CPC分类号： H01L21/565 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00

摘要： An integrated circuit chip package comprising a lead frame having an integrated circuit die electrically connected thereto. Partially encapsulating the lead frame and the integrated circuit die is a package body. The package body includes the central portion which is circumvented by a peripheral portion defining opposed top and bottom surfaces. Disposed in at least one of the top and bottom surfaces of the peripheral portion of the package body is a singulation crease. The singulation crease, which is formed in the package body during its molding process, is used to provide a stress concentration line which reduces stress along the edge of the chip package and avoids chipping and cracking problems during the punch singulation process used to complete the manufacture of the same.

摘要翻译： 一种集成电路芯片封装，包括具有与其电连接的集成电路管芯的引线框架。 引线框架和集成电路管芯的部分封装是封装体。 包装体包括由限定相对的顶表面和底表面的周边部分围绕的中心部分。 在包装体的周边部分的顶表面和底表面中的至少一个中设置有单切折痕。 在成型过程中在封装体中形成的分割折痕用于提供应力集中线，其减小沿着芯片封装边缘的应力，并避免在用于完成制造的冲压分离过程中的切屑和开裂问题 一样的。

公开(公告)号：US08300423B1

公开(公告)日：2012-10-30

申请号：US12787238

申请日：2010-05-25

申请人： Robert Francis Darveaux ,  Ludovico Bancod ,  Akito Yoshida

发明人： Robert Francis Darveaux ,  Ludovico Bancod ,  Akito Yoshida

IPC分类号： H01R9/00 ,  H01K1/18

CPC分类号： H01L25/105 ,  H01L23/5389 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014

摘要： A method of forming a stackable treated via package includes coupling interconnection balls to terminals. The interconnection balls are encapsulated in a package body. Via apertures are formed in the package body to expose the interconnection balls. The interconnection balls are treated to form treated interconnection balls comprising treated surfaces. The treated interconnection balls of the stackable treated via package enhance bonding with interconnection balls of a stacked electronic component package thus maximizing yield.

摘要翻译： 形成可堆叠处理的通孔封装的方法包括将互连球耦合到端子。 互连球被封装在封装体内。 在封装体中形成通孔，以露出互连球。 对互连球进行处理，以形成包括处理过的表面的经处理的互连球。 可堆叠处理的通孔封装的经处理的互连球增强了与堆叠的电子部件封装的互连球的粘合，从而使产量最大化。

公开(公告)号：US20070176287A1

公开(公告)日：2007-08-02

申请号：US10812274

申请日：2004-03-29

申请人： Sean Crowley ,  Ludovico Bancod ,  Terry Davis ,  Robert Darveaux ,  Michael Gaynor

发明人： Sean Crowley ,  Ludovico Bancod ,  Terry Davis ,  Robert Darveaux ,  Michael Gaynor

IPC分类号： H01L23/34

CPC分类号： H01L23/3121 ,  H01L23/66 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package comprising a non-conductive film which defines opposed top and bottom film surfaces and includes a plurality of vias disposed therein. Disposed on the top film surface is a plurality of upper leads which circumvent respective ones of the vias. Similarly, disposed on the bottom film surface is a plurality of lower leads which circumvent respective ones of the vias and are electrically connected to respective ones of the upper leads. At least one transmission line element is also disposed on the top film surface and electrically connected to at least one of the upper leads. Attached to the top film surface and electrically connected to at least one of the upper leads and the transmission line element is at least one semiconductor die. A package body at least partially covers the semiconductor die, the upper leads, the transmission line element, and the top film surface.

摘要翻译： 一种半导体封装，其包括限定相对的顶部和底部膜表面的非导电膜，并且包括设置在其中的多个通孔。 设置在顶部薄膜表面上的是多个上引线，其绕过各个通孔。 类似地，设置在底部薄膜表面上的是多个下引线，其围绕相应的通孔并电连接到相应的上引线。 至少一个传输线元件也设置在顶部膜表面上并电连接到至少一个上部引线。 连接到顶部膜表面并电连接到上引线和传输线元件中的至少一个是至少一个半导体管芯。 封装体至少部分地覆盖半导体管芯，上部引线，传输线元件和顶部膜表面。

公开(公告)号：US06339252B1

公开(公告)日：2002-01-15

申请号：US09593269

申请日：2000-06-13

申请人： Eulogia A. Niones ,  Nhun Thun Kham ,  Ludovico Bancod ,  Yeon Ho Choi ,  Sean T. Crowley

发明人： Eulogia A. Niones ,  Nhun Thun Kham ,  Ludovico Bancod ,  Yeon Ho Choi ,  Sean T. Crowley

IPC分类号： H01L23495

CPC分类号： H01L23/49524 ,  H01L23/49558 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： The present invention includes a package for housing an integrated circuit device. The present invention also includes leadframes and methods for making such packages. In one embodiment, the package includes an integrated circuit device on a metal die pad. A metal ring is between the die pad and leads and surrounds the die pad. The ring is connected to the die pad by a nonconductive adhesive tape. Encapsulant material covers the entire structure, except for portions of the leads. The ring is electrically connected to a lead identified for connection to an external power voltage supply. The ring in turn is electrically connected to a power voltage input pad on the integrated circuit device. The potential of the die pad may float, or the die pad may be electrically connected through a lead to an external ground voltage. The package is made from a leadframe that has a die pad, a metal ring between the die pad and radiating leads, and a nonconductive adhesive tape that connects the ring to the die pad. A bypass capacitor may be electrically connected between the die pad and ring.

摘要翻译： 本发明包括用于容纳集成电路器件的封装。 本发明还包括用于制造这种包装的引线框架和方法。 在一个实施例中，封装包括在金属管芯焊盘上的集成电路器件。 金属环位于管芯焊盘和引线之间并且围绕管芯焊盘。 环通过非导电胶带连接到管芯焊盘。 除了引线的部分之外，密封材料覆盖整个结构。 该环电连接到被识别用于连接到外部电源电压的引线。 环依次与集成电路器件上的电源电压输入焊盘电连接。 芯片焊盘的电位可能浮动，或者芯片焊盘可以通过引线电连接到外部接地电压。 封装由引线框架制成，引线框架具有管芯焊盘，管芯焊盘和辐射引线之间的金属环，以及将环连接到管芯焊盘的非导电胶带。 旁路电容器可以电连接在管芯焊盘和环之间。

公开(公告)号：US06258629B1

公开(公告)日：2001-07-10

申请号：US09370600

申请日：1999-08-09

申请人： Eulogia A. Niones ,  Nhun Thun Kham ,  Ludovico Bancod ,  Yeon Ho Choi ,  Sean T. Crowley

发明人： Eulogia A. Niones ,  Nhun Thun Kham ,  Ludovico Bancod ,  Yeon Ho Choi ,  Sean T. Crowley

IPC分类号： H01L2144

CPC分类号： H01L23/49524 ,  H01L23/49558 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： The present invention includes a package for housing an integrated circuit device. The present invention also includes leadframes and methods for making such packages. The package includes an integrated circuit device on a metal die pad. A metal ring is between the die pad and leads and surrounds the die pad. The ring is connected to the die pad by a nonconductive tape. Encapsulant material covers the entire structure. The ring is connected to a lead identified for connection to an external power voltage supply. The ring in turn is connected to a power voltage input pad on the integrated circuit device. The die pad floats, or is connected to a lead that is connected to an external ground voltage. The package is made from a leadframe that has a die pad, a metal ring between the die pad and radiating leads, and a nonconductive tape that connects the ring to the die pad. In one embodiment, the leadframe and package also include a bypass or decoupling capacitor attached between the die pad and the ring.

摘要翻译： 本发明包括用于容纳集成电路器件的封装。 本发明还包括用于制造这种包装的引线框架和方法。 该封装包括在金属管芯焊盘上的集成电路器件。 金属环位于管芯焊盘和引线之间并且围绕管芯焊盘。 环通过非导电带连接到管芯焊盘。 封装材料覆盖整个结构。 环连接到与外部电源电压连接的识别导线。 该环依次连接到集成电路设备上的电源电压输入焊盘。 芯片焊盘浮动，或连接到连接到外部接地电压的引线。 封装由引线框制成，引线框具有管芯焊盘，管芯焊盘和辐射引线之间的金属环，以及将环连接到管芯焊盘的非导电带。 在一个实施例中，引线框和封装还包括附接在管芯焊盘和环之间的旁路或去耦电容器。