公开(公告)号：US06599840B2

公开(公告)日：2003-07-29

申请号：US10194833

申请日：2002-07-11

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

公开(公告)号：US06596642B2

公开(公告)日：2003-07-22

申请号：US10193801

申请日：2002-07-11

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

公开(公告)号：US06580114B1

公开(公告)日：2003-06-17

申请号：US09497935

申请日：2000-02-04

申请人： Thomas M Graettinger ,  Paul J. Schuele ,  Pierre C. Fazan ,  Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh ,  Thomas Arthur Figura

发明人： Thomas M Graettinger ,  Paul J. Schuele ,  Pierre C. Fazan ,  Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh ,  Thomas Arthur Figura

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/84

摘要： Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void. In another aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure only partially filling in the void to provide a tubular structure.

摘要翻译： 描述形成电容器的电容器和方法。 根据一个实施方案，在衬底节点位置上形成电容器开口。 随后在电容器开口内形成导电材料，并与节点位置进行电连接。 在电容器开口内形成突出的绝缘结构，并且包括一个侧面外表面，其外表面的至少一部分由邻近的导电材料支撑并向下垂直延伸。 第一和第二电容器板及其之间的电介质层形成在电容器开口内并由突出结构支撑。 在一个方面，导电材料被形成为占据小于全部电容器开口并且在其中留下空隙，其中突起结构基本上如果不是完全填充在空隙中。 另一方面，导电材料被形成为占据小于全部电容器开口并且在其中留下空隙，其中突出结构仅部分地填充在空隙中以提供管状结构。

公开(公告)号：US06495471B2

公开(公告)日：2002-12-17

申请号：US09785728

申请日：2001-02-16

申请人： Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh

发明人： Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh

IPC分类号： H01L2100

CPC分类号： H01L21/76802 ,  H01L21/31111 ,  H01L21/76831 ,  H01L21/76841 ,  H01L21/76897

摘要： The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material. Where the buffer layer is of a conductive layer, the effect of the second etch is that the insulative layer is substantially undercut due to the etching of the buffer layer and due to selectivity to all other etch-exposed structures upon the semiconductor substrate. The undercut leaves a laterally-oriented second cavity within which lateral surfaces of the buffer layer are exposed. Following the second etch, a method of covering the laterally exposed surfaces of the buffer layer, exposed by the undercut, is chosen in order to isolate the remaining laterally exposed surfaces of the buffer layer. These methods include reflowing the insulative layer to cover the laterally exposed surfaces of the buffer layer, and forming a liner layer in the cavity to cover the laterally exposed surfaces of the buffer layer.

摘要翻译： 本发明涉及构建其中半导体衬底上具有用于缓冲层将用作蚀刻均匀性辅助的处理方法中的蚀刻缓冲层的微电子器件。 在制造微电子器件的方法中，用蚀刻缓冲层和绝缘层覆盖半导体衬底。 通过掩模进行图案化和蚀刻来进行第一蚀刻。 第一蚀刻穿透绝缘层，在其中形成空腔，并且对缓冲层是选择性的，以便露出缓冲层。 执行对绝缘层和半导体衬底具有选择性的第二蚀刻，并且对缓冲层不是选择性的。 缓冲层可以是除了绝缘层的材料以外的类型的绝缘材料，或者缓冲层也可以是导电材料。 在缓冲层是导电层的情况下，第二蚀刻的效果是由于缓冲层的蚀刻以及由于对半导体衬底上的所有其它蚀刻暴露结构的选择性而导致的绝缘层基本上被切下。 底切留下横向定向的第二腔，其中缓冲层的侧表面露出。 在第二蚀刻之后，选择覆盖由底切暴露的缓冲层的横向暴露的表面的方法，以便隔离缓冲层的剩余横向暴露的表面。 这些方法包括回流绝缘层以覆盖缓冲层的横向暴露的表面，以及在空腔中形成衬层以覆盖缓冲层的横向暴露的表面。

公开(公告)号：US06461967B2

公开(公告)日：2002-10-08

申请号：US09907296

申请日：2001-07-16

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

摘要翻译： 公开了用于从具有对材料的低应力部分选择性的材料去除工艺从含硅和/或含锗材料形成成形结构的方法。 通常，该方法最初在半导体衬底上提供一层材料。 然后，其中具有均匀应力的材料被掩蔽，并且材料的一部分中的应力例如通过将离子注入未掩模部分中而减少。 去除掩模，并且优选通过蚀刻工艺选择性地去除材料的高应力掩蔽部分。 材料的低应力部分保留并形成成形结构。 一种优选的选择性蚀刻方法使用基本蚀刻剂。 各种方法用于形成凸起形状的结构，成形开口，多晶硅插塞，电容器存储节点，环绕栅极晶体管，独立壁，互连线，沟槽电容器和沟槽隔离区域。

公开(公告)号：US06303434B1

公开(公告)日：2001-10-16

申请号：US09510709

申请日：2000-02-22

申请人： Kunal R. Parekh ,  Zhiqiang Wu ,  Li Li

发明人： Kunal R. Parekh ,  Zhiqiang Wu ,  Li Li

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82

摘要： A method of making a capacitor comprising providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical structures and within the trench. Portions of the hard mask layer and the second group of the alternating layers of doped polysilicon and undoped polysilicon are selectively removed. An etch selective to the doped polysilicon is performed to selectively remove the undoped polysilicon to create a structure with spaced apart doped polysilicon layers. A dielectric layer and an electrically conductive cell plate are formed over the alternating layers of the doped polysilicon and the undoped polysilicon. The semiconductor substrate is heated to diffuse dopant in the doped polysilicon into the undoped polysilicon. The resultant novel capacitor has a fin-like structure extending therefrom which increases the surface area thereof.

摘要翻译： 一种制造电容器的方法，包括提供在半导体衬底上的一对栅极堆叠之间延伸的空间，该空间暴露半导体衬底上的电荷传导区域。 在一对栅极叠层上形成BPSG层。 在沉积多晶硅的单个沉积循环期间，在BPSG层上形成包括掺杂多晶硅和未掺杂多晶硅交替层的硬掩模层。 选择性地去除硬掩模层和BPSG层的部分以形成在栅叠层之上延伸并且在它们之间具有沟槽的拓扑结构。 执行间隔物蚀刻和接触蚀刻以暴露电荷导电区域。 在每个形貌结构的侧面上形成掺杂的多晶硅间隔物。 掺杂多晶硅和未掺杂多晶硅的第二组交替层形成在拓扑结构之上和沟槽内。 选择性地去除了硬掩模层和掺杂多晶硅和未掺杂多晶硅的交替层的第二组的部分。 执行对掺杂多晶硅选择性的蚀刻以选择性地去除未掺杂的多晶硅以产生具有间隔开的掺杂多晶硅层的结构。 在掺杂多晶硅和未掺杂多晶硅的交替层上形成介电层和导电单元板。 加热半导体衬底以将掺杂多晶硅中的掺杂剂扩散到未掺杂的多晶硅中。 所得到的新型电容器具有从其延伸的鳍状结构，其增加其表面积。

公开(公告)号：US06261964B1

公开(公告)日：2001-07-17

申请号：US09205989

申请日：1998-12-04

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

摘要翻译： 公开了用于从具有对材料的低应力部分选择性的材料去除工艺从含硅和/或含锗材料形成成形结构的方法。 通常，该方法最初在半导体衬底上提供一层材料。 然后，其中具有均匀应力的材料被掩蔽，并且材料的一部分中的应力例如通过将离子注入未掩模部分中而减少。 去除掩模，并且优选通过蚀刻工艺选择性地去除材料的高应力掩蔽部分。 材料的低应力部分保留并形成成形结构。 一种优选的选择性蚀刻方法使用基本蚀刻剂。 各种方法用于形成凸起形状的结构，成形开口，多晶硅插塞，电容器存储节点，环绕栅极晶体管，独立壁，互连线，沟槽电容器和沟槽隔离区域。

公开(公告)号：US06331720B1

公开(公告)日：2001-12-18

申请号：US09511514

申请日：2000-02-22

申请人： Kunal R. Parekh ,  Zhiqiang Wu ,  Li Li

发明人： Kunal R. Parekh ,  Zhiqiang Wu ,  Li Li

IPC分类号： H01L2708

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82

摘要： An electrically conductive structure, such as a capacitor is disclosed. A capacitor can be made by providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical strictures and within the trenches. Portions of the hard mask layer and the second group of the alternating layers of doped polysilicon and undoped polysilicon are selectively removed. An etch selective to the doped polysilicon is performed to selectively remove the undoped polysilicon to create an electrically conductive structure with spaced apart doped polysilicon layers. A dielectric layer and an electrically conductive cell plate are formed over the alternating layers of the doped polysilicon and the undoped polysilicon. The semiconductor substrate is heated to diffuse dopant in the doped polysilicon into the undoped polysilicon. The resultant novel capacitor has fin-like structure extending therefrom which increase the surface area thereof.

摘要翻译： 公开了诸如电容器的导电结构。 可以通过在半导体衬底上的一对栅极堆叠之间提供延伸的空间来形成电容器，该空间暴露半导体衬底上的电荷导电区域。 在一对栅极叠层上形成BPSG层。 在沉积多晶硅的单个沉积循环期间，在BPSG层上形成包括掺杂多晶硅和未掺杂多晶硅交替层的硬掩模层。 选择性地去除硬掩模层和BPSG层的部分以形成在栅叠层之上延伸并且在它们之间具有沟槽的拓扑结构。 执行间隔物蚀刻和接触蚀刻以暴露电荷导电区域。 在每个形貌结构的侧面上形成掺杂的多晶硅间隔物。 掺杂多晶硅和未掺杂多晶硅的第二组交替层形成在形貌上的狭缝和沟槽内。 选择性地去除了硬掩模层和掺杂多晶硅和未掺杂多晶硅的交替层的第二组的部分。 执行对掺杂多晶硅的选择性蚀刻以选择性地去除未掺杂的多晶硅以产生具有间隔开的掺杂多晶硅层的导电结构。 在掺杂多晶硅和未掺杂多晶硅的交替层上形成介电层和导电单元板。 加热半导体衬底以将掺杂多晶硅中的掺杂剂扩散到未掺杂的多晶硅中。 所得到的新型电容器具有从其延伸的鳍状结构，其增加其表面积。

公开(公告)号：US06596648B2

公开(公告)日：2003-07-22

申请号：US10193850

申请日：2002-07-11

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

公开(公告)号：US06191047B1

公开(公告)日：2001-02-20

申请号：US09597189

申请日：2000-06-20

申请人： Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh

发明人： Li Li ,  Zhiqiang Wu ,  Kunal R. Parekh

IPC分类号： H01L2100

CPC分类号： H01L21/76802 ,  H01L21/31111 ,  H01L21/76831 ,  H01L21/76841 ,  H01L21/76897

摘要： The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material. Where the buffer layer is of a conductive layer, the effect of the second etch is that the insulative layer is substantially undercut due to the etching of the buffer layer and due to selectivity to all other etch-exposed structures upon the semiconductor substrate. The undercut leaves a laterally-oriented second cavity within which lateral surfaces of the buffer layer are exposed. Following the second etch, a method of covering the laterally exposed surfaces of the buffer layer, exposed by the undercut, is chosen in order to isolate the remaining laterally exposed surfaces of the buffer layer. These methods include reflowing the insulative layer to cover the laterally exposed surfaces of the buffer layer, and forming a liner layer in the cavity to cover the laterally exposed surfaces of the buffer layer.

摘要翻译： 本发明涉及构建其中半导体衬底上具有用于缓冲层将用作蚀刻均匀性辅助的处理方法中的蚀刻缓冲层的微电子器件。 在制造微电子器件的方法中，用蚀刻缓冲层和绝缘层覆盖半导体衬底。 通过掩模进行图案化和蚀刻来进行第一蚀刻。 第一蚀刻穿透绝缘层，在其中形成空腔，并且对缓冲层是选择性的，以便露出缓冲层。 执行对绝缘层和半导体衬底具有选择性的第二蚀刻，并且对缓冲层不是选择性的。 缓冲层可以是除了绝缘层的材料以外的类型的绝缘材料，或者缓冲层也可以是导电材料。 在缓冲层是导电层的情况下，第二蚀刻的效果是由于缓冲层的蚀刻以及由于对半导体衬底上的所有其它蚀刻暴露结构的选择性而导致的绝缘层基本上被切下。 底切留下横向定向的第二腔，其中缓冲层的侧表面露出。 在第二蚀刻之后，选择覆盖由底切暴露的缓冲层的横向暴露的表面的方法，以便隔离缓冲层的剩余横向暴露的表面。 这些方法包括回流绝缘层以覆盖缓冲层的横向暴露的表面，以及在空腔中形成衬层以覆盖缓冲层的横向暴露的表面。