公开(公告)号：US5999032A

公开(公告)日：1999-12-07

申请号：US35053

申请日：1998-03-05

Applicant: Gyh-Bin Wang ,  Li-Chin Tien

Inventor： Gyh-Bin Wang ,  Li-Chin Tien

IPC: G06F1/10 ,  H03K5/14 ,  H03L7/00

CPC classification number: G06F1/10

Abstract: A dual phase synchronous race delay clock circuit that will create an internal clock signal in an integrated circuit that is synchronized with and has minimum skew from an external system clock signal is disclosed. The synchronous race delay circuit has an input buffer circuit to receive, buffer, and amplify an external clock signal. The input buffer circuit has a delay time that is the first delay time. A fast pulse generator is connected to the input buffer circuit to create a fast pulse signal. The fast pulse generator is connected to a slow pulse generator to create a slow pulse signal. The fast pulse generator and the slow pulse generator is connected to a race delay measurement means to determine a measurement of a period of the external system clock by comparing a time difference between the slow pulse signal and a following fast pulse signal. A delay control means is connected to the race delay measurement means to receive the measurement of the period of the external system clock. The delay control means will create a first phase control pulse and a second phase control pulse. A duty cycle synchronizer means is connected to the delay control means to create the dual phases of the internal clock from the first phase control pulse and the second phase control pulse. An internal buffer will buffer and amplify the two phases of the internal clock signal that is aligned with the external clock signal to have minimum skew.

Abstract translation: 公开了一种双相同步竞争延迟时钟电路，其将在与外部系统时钟信号同步并且具有来自外部系统时钟信号的最小偏移的集成电路中创建内部时钟信号。 同步竞争延迟电路具有用于接收，缓冲和放大外部时钟信号的输入缓冲电路。 输入缓冲电路具有作为第一延迟时间的延迟时间。 快速脉冲发生器连接到输入缓冲电路以产生快速脉冲信号。 快速脉冲发生器连接到慢脉冲发生器以产生慢脉冲信号。 快速脉冲发生器和慢脉冲发生器通过比较慢脉冲信号和随后的快速脉冲信号之间的时间差，连接到比赛延迟测量装置，以确定外部系统时钟周期的测量。 延迟控制装置连接到比赛延迟测量装置以接收外部系统时钟周期的测量。 延迟控制装置将产生第一相位控制脉冲和第二相位控制脉冲。 占空比同步器装置连接到延迟控制装置，以从第一相位控制脉冲和第二相位控制脉冲产生内部时钟的双相位。 内部缓冲器将缓冲和放大与外部时钟信号对准的内部时钟信号的两相，以具有最小的偏移。

公开(公告)号：US08754656B2

公开(公告)日：2014-06-17

申请号：US13410472

申请日：2012-03-02

Applicant: Tah-Kang Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang ,  Chun-Peng Wu ,  Li-Chin Tien

Inventor： Tah-Kang Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang ,  Chun-Peng Wu ,  Li-Chin Tien

IPC: G01R27/28 ,  G11C29/10 ,  G06F11/00 ,  G01R31/3193 ,  G11C29/50 ,  G11C29/02 ,  G01R31/317

CPC classification number: G01R31/31932 ,  G01R31/31727 ,  G11C29/022 ,  G11C29/50012

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract translation: 高速测试电路从测试仪接收测试仪时钟，并对被测电路进行测试。 高速测试电路根据测试仪时钟产生高频时钟，因此能够在两个频率下工作。 高速测试电路根据高频时钟测试被测电路，并根据例如测试仪时钟的低频时钟执行低速运行。

公开(公告)号：US5923613A

公开(公告)日：1999-07-13

申请号：US40435

申请日：1998-03-18

Applicant: Li-Chin Tien ,  Gyh-Bin Wang

Inventor： Li-Chin Tien ,  Gyh-Bin Wang

IPC: G11C7/22 ,  G11C8/00

CPC classification number: G11C7/22

Abstract: A multiple phase latched type synchronized clock circuit that will create a multiple phases of an internal clock signal in an integrated circuit that is synchronized with an external system clock signal is disclosed. A latched type clock synchronizer circuit has an input buffer circuit to receive the external input clock to create a first timing clock. The input buffer is connected to a delay monitor circuit to delay the first timing clock by a first delay factor to create a second timing clock. A delay measurement latch array is connected to the input buffer circuit and the delay monitor circuit to create a latched measurement signal, which indicates a period of time between a second pulse of the first timing clock and a first pulse of the second timing clock. A multiple delay array is connected to the input buffer to receive the first timing clock and will create multiple pluralities of incrementally delayed timing clocks. The multiple pluralities of incrementally delay timing clocks and the latched measurement signal are the inputs to a plurality of phase generators that create a plurality of third timing clocks. Each of a plurality of internal buffers is connected to each of the phase generators to receive one of the third timing clocks. The third timing clock is shaped to create one of the multiple phases of the internal clocks which are then buffered, amplified and transmitted to the integrated circuit.

Abstract translation: 公开了一种多相锁存型同步时钟电路，其将在与外部系统时钟信号同步的集成电路中产生内部时钟信号的多个相位。 锁存型时钟同步器电路具有输入缓冲电路，用于接收外部输入时钟以产生第一定时时钟。 输入缓冲器连接到延迟监视器电路，以将第一定时时钟延迟第一延迟因子以产生第二定时时钟。 延迟测量锁存阵列连接到输入缓冲器电路和延迟监视电路，以产生锁存的测量信号，其表示第一定时时钟的第二脉冲与第二定时时钟的第一脉冲之间的一段时间。 多个延迟阵列连接到输入缓冲器以接收第一定时时钟，并且将产生多个递增延迟的定时时钟。 多个增量延迟定时时钟和锁存的测量信号是产生多个第三定时时钟的多个相位发生器的输入。 多个内部缓冲器中的每一个连接到每个相位发生器以接收第三定时时钟中的一个。 第三定时时钟被形成为产生内部时钟的多个相位中的一个，然后被缓冲，放大并传输到集成电路。

公开(公告)号：US20120229146A1

公开(公告)日：2012-09-13

申请号：US13410472

申请日：2012-03-02

Applicant: Tah-Kang Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang ,  Chun-Peng Wu ,  Li-Chin Tien

Inventor： Tah-Kang Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang ,  Chun-Peng Wu ,  Li-Chin Tien

IPC: G01R27/28

CPC classification number: G01R31/31932 ,  G01R31/31727 ,  G11C29/022 ,  G11C29/50012

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract translation: 高速测试电路从测试仪接收测试仪时钟，并对被测电路进行测试。 高速测试电路根据测试仪时钟产生高频时钟，因此能够在两个频率下工作。 高速测试电路根据高频时钟测试被测电路，并根据例如测试仪时钟的低频时钟执行低速运行。

公开(公告)号：US06429710B1

公开(公告)日：2002-08-06

申请号：US08709896

申请日：1996-09-09

Applicant: Tah-Kang Joseph Ting ,  Gyh-Bin Wang ,  Chien-Te Wu

Inventor： Tah-Kang Joseph Ting ,  Gyh-Bin Wang ,  Chien-Te Wu

IPC: H03K3037

CPC classification number: H03K3/3565

Abstract: An improved input buffer circuit of the type having a chain of FET inverter circuits has an FET connected in a feedback loop that functions like a Schmidt trigger and counteracts a hysteresis effect that causes variations in the delay of the inverter circuits and compensation for process variation. An FET is connected to conduct in its source-drain circuit between one of the power supply terminals and the interconnection node of two of the inverters in the chain. The gate of FET is connected to receive a signal from the output of one of the inverters. The hysteresis effect is characterized by different rising and falling paths at one knee of the transfer curve that describes the switching operation. The channel type of the FET and the polarity of the power supply terminal are selected to provide feedback during the transition where the knee occurs.

Abstract translation: 具有FET反相器电路链的类型的改进的输入缓冲器电路具有连接在反馈环路中的FET，其功能类似于施密特触发器，并抵消引起逆变器电路的延迟变化和过程变化补偿的滞后效应。 连接FET连接在链路中的两个逆变器的一个电源端子和互连节点之间的源极 - 漏极电路中。 FET的栅极被连接以从其中一个逆变器的输出接收信号。 滞后效应的特征在于描述开关操作的传输曲线的一个拐点处的不同的上升和下降路径。 选择FET的通道类型和电源端子的极性以在膝盖发生的转变期间提供反馈。

公开(公告)号：US06543015B1

公开(公告)日：2003-04-01

申请号：US09336785

申请日：1999-06-21

Applicant: Gyh-Bin Wang ,  Der-Min Yuan

Inventor： Gyh-Bin Wang ,  Der-Min Yuan

IPC: G06F1100

CPC classification number: G11C29/40

Abstract: In this invention two compression circuits are combined to produce at a single output pass/fail condition for a plurality of memory addresses and a plurality of I/O. The output of an address compression circuit is connected to an I/O circuit. An I/O compression circuit is connected to several I/O circuits and the output of the I/O compression circuit controls a selected data output driver to provide a combined test result of the plurality of addresses and the plurality of I/O. The combination of the two compression circuits is made possible because the address data compression circuits and the I/O compression circuits use different truth tables.

Abstract translation: 在本发明中，两个压缩电路被组合以产生用于多个存储器地址和多个I / O的单个输出通过/失败条件。 地址压缩电路的输出连接到I / O电路。 I / O压缩电路连接到多个I / O电路，I / O压缩电路的输出控制所选择的数据输出驱动器，以提供多个地址和多个I / O的组合测试结果。 两个压缩电路的组合是可能的，因为地址数据压缩电路和I / O压缩电路使用不同的真值表。

公开(公告)号：US07961966B2

公开(公告)日：2011-06-14

申请号：US11028744

申请日：2005-01-04

Applicant: Gyh-Bin Wang ,  Wen-Ming Lu

Inventor： Gyh-Bin Wang ,  Wen-Ming Lu

IPC: G06K9/40 ,  G06K9/00 ,  H04N5/228

CPC classification number: H04N5/23248

Abstract: A method and an apparatus are provided for image stabilization for the output of analog-to-digital converters (ADC) and for phase-locked loops (PLL). The digital coding at the output of ADCs and PLLs is filtered by this method and apparatus to eliminate the noise which has contaminated the coding. The noise sources are noise picked up by the cable, system board noise, ADC power and ground noise paths, and switching noise. The differences of energy level of sequential pixels in the ADC and PLL digital outputs used in image displays are used to decide if correction is required. The method of image noise filtering is compatible with programmable circuitry. This allows the method to be tuned for optimal image stabilization.

Abstract translation: 提供了用于模数转换器（ADC）和锁相环（PLL）的输出的图像稳定的方法和装置。 通过该方法和装置对ADC和PLL输出端的数字编码进行滤波，以消除已经污染编码的噪声。 噪声源是由电缆拾取的噪声，系统板噪声，ADC功率和接地噪声路径以及开关噪声。 在图像显示中使用的ADC和PLL数字输出中的顺序像素的能级差异用于确定是否需要校正。 图像噪声滤波的方法与可编程电路兼容。 这样可以调整该方法以获得最佳图像稳定性。

公开(公告)号：US20090009224A1

公开(公告)日：2009-01-08

申请号：US11976631

申请日：2007-10-26

Applicant: Gyh-Bin Wang ,  Ying-Chieh Huang

Inventor： Gyh-Bin Wang ,  Ying-Chieh Huang

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/0891 ,  H03L7/10

Abstract: The invention discloses a new architecture of multiphase delay-locked loop (DLL) with innovative 3-edge phase detector (3-edge PD), which compares the VCDL's first delay interval and the last delay interval to send an Up pulse or a Dn pulse to adjust the interval among those delay clock phases. The DLL may achieve both wide-range operation and multiple clock phase generation, and is also immune to multi-selection problem.

Abstract translation: 本发明公开了一种具有创新的3边缘相位检测器（3边缘PD）的多相延迟锁定环路（DLL）的新架构，其比较了VCDL的第一个延迟间隔和最后一个延迟间隔，以发送Up脉冲或Dn脉冲 以调整这些延迟时钟相位之间的间隔。 DLL可以实现宽范围操作和多时钟相位生成，并且也免受多选择问题的影响。

公开(公告)号：US06943783B1

公开(公告)日：2005-09-13

申请号：US10005807

申请日：2001-12-05

Applicant: Tah-Kang Joseph Ting ,  Yin-Shing Lieu ,  Gyh-Bin Wang ,  Ming-Song Hwang

Inventor： Tah-Kang Joseph Ting ,  Yin-Shing Lieu ,  Gyh-Bin Wang ,  Ming-Song Hwang

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G09G3/3611 ,  G09G2310/0229 ,  G09G2310/08 ,  G09G2340/0485

Abstract: This invention provides a method and apparatus for displaying an unscaled image frame on an LCD panel. The method and apparatus uses the same line buffers available to the digital signal processor DSP formerly used for scaling the displayed image up or down in size. No extra frame buffers are required by this invention since the frame rates of the source image and the LCD panel are the same. The image frame buffer is written to the LCD panel on every other panel vertical synchronization pulse. The vertical synchronization timing is shifted to the left or right in the time domain to center the image on the LCD panel.

Abstract translation: 本发明提供了一种用于在LCD面板上显示未缩放图像帧的方法和装置。 该方法和装置使用以前用于大小缩放显示图像的数字信号处理器DSP可用的相同行缓冲器。 由于源图像和LCD面板的帧速率相同，本发明不需要额外的帧缓冲器。 每隔一个面板垂直同步脉冲将图像帧缓冲区写入LCD面板。 垂直同步定时在时域中向左或向右移动，使图像在LCD面板上居中。

公开(公告)号：US06791382B1

公开(公告)日：2004-09-14

申请号：US10117951

申请日：2002-04-08

Applicant: Tah-Kang Joseph Ting ,  Gyh-Bin Wang ,  Ming-Song Huang

Inventor： Tah-Kang Joseph Ting ,  Gyh-Bin Wang ,  Ming-Song Huang

IPC: H03L706

CPC classification number: G09G5/008 ,  G09G3/3611 ,  G09G2310/08 ,  G09G2330/06 ,  H03L7/197 ,  H04N5/21

Abstract: A method to reduce clock noise in a multiple clock circuit is achieved. The method comprises, first, providing a periodic signal. Next, a first clock signal is provided having a frequency that is a constant multiple of the frequency of the periodic signal. Finally, a second clock signal is derived from the periodic signal. The second clock signal has a frequency that is a non-constant multiple of the periodic signal frequency. The non-constant multiple comprises the sum of a constant value plus a time-varying value. The spectral energy at the sum and difference frequencies of the first and second clock signals is reduced by frequency distribution spreading. A circuit is achieved comprising the above method.

Abstract translation: 实现了减少多时钟电路中的时钟噪声的方法。 该方法包括：首先提供周期信号。 接下来，提供具有作为周期信号的频率的恒定倍数的频率的第一时钟信号。 最后，从周期信号导出第二时钟信号。 第二时钟信号具有作为周期信号频率的非常数倍的频率。 非常数倍数包括恒定值加上时变值的和。 第一和第二时钟信号的和频和差频的频谱能量通过频率分布扩展而减小。 实现了包括上述方法的电路。