摘要:
Resources of a partitionable computer system are partitioned into at least first and second partitions, in accordance with a first or second mode of operation of the partitionable computer system. The system is run in the first or second mode, partitioned in accordance with the partitioning step. Periodically, it is determined whether the computer system should be switched from one mode to the other mode. If so, the computer system is run in the other mode, partitioned in accordance with the other mode. The first and second modes of operation are defined in accordance with historical observations of the partitionable computer system. The periodic determination is carried out based on predictions in accordance with the historical observations.
摘要:
Resources of a partitionable computer system are partitioned into at least first and second partitions, in accordance with a first or second mode of operation of the partitionable computer system. The system is run in the first or second mode, partitioned in accordance with the partitioning step. Periodically, it is determined whether the computer system should be switched from one mode to the other mode. If so, the computer system is run in the other mode, partitioned in accordance with the other mode. The first and second modes of operation are defined in accordance with historical observations of the partitionable computer system. The periodic determination is carried out based on predictions in accordance with the historical observations.
摘要:
Resources of a partitionable computer system are partitioned into: (i) a first partition for first jobs, the first jobs being at least one of small and short running; and (ii) a second partition for second jobs, the second jobs being at least one of large and long running. The computer system is run as partitioned in the partitioning step and the partitioning is periodically re-evaluated against at least one threshold for at least one of the partitions. If the periodic re-evaluation suggests that one of the first and second partitions is underutilized, the resources of the partitionable computer system are dynamically re-partitioned to reassign at least some of the resources of the partitionable computer system from the underutilized one of the first and second partitions to another one of the first and second partitions
摘要:
Resources of a partitionable computer system are partitioned into: (i) a first partition for first jobs, the first jobs being at least one of small and short running; and (ii) a second partition for second jobs, the second jobs being at least one of large and long running. The computer system is run as partitioned in the partitioning step and the partitioning is periodically re-evaluated against at least one threshold for at least one of the partitions. If the periodic re-evaluation suggests that one of the first and second partitions is underutilized, the resources of the partitionable computer system are dynamically re-partitioned to reassign at least some of the resources of the partitionable computer system from the underutilized one of the first and second partitions to another one of the first and second partitions.
摘要:
Operand liveness state information is maintained during context switches for current architected operands of executing programs. The current operand state information indicates whether corresponding current operands are enabled or disabled for use by a first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands. A machine instruction of the first program module accesses a current operand by using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.
摘要:
Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).
摘要:
A prefix instruction is executed and passes operands to a net instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a target register of the prefix instruction execution.
摘要:
Consolidating problem tickets for a multi-tiered application may comprise identifying a plurality of correlated virtual machines that are running one or more application components of the multi-tiered application. Problem reports may be identified that are generated by one or more of the plurality of correlated virtual machines and caused by a failure of a same single component of the multi-tiered application. The identified problem reports may be consolidated into a single ticket and placed into a ticket handling system.
摘要:
A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.
摘要:
Mechanisms for performing a scattered load operation are provided. With these mechanisms, an extended address is received in a cache memory of a processor. The extended address has a plurality of data element address portions that specify a plurality of data elements to be accessed using the single extended address. Each of the plurality of data element address portions is provided to corresponding data element selector logic units of the cache memory. Each data element selector logic unit in the cache memory selects a corresponding data element from a cache line buffer based on a corresponding data element address portion provided to the data element selector logic unit. Each data element selector logic unit outputs the corresponding data element for use by the processor.