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    Method to improve wet etch budget in FEOL integration
    1.
    发明授权
    Method to improve wet etch budget in FEOL integration 有权
    在FEOL集成中改善湿法蚀刻预算的方法

    公开(公告)号：US08232179B2

    公开(公告)日：2012-07-31

    申请号：US12571483

    申请日：2009-10-01

    申请人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    发明人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229

    摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

    摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

    BORDERLESS CONTACT FOR REPLACEMENT GATE EMPLOYING SELECTIVE DEPOSITION
    2.
    发明申请
    BORDERLESS CONTACT FOR REPLACEMENT GATE EMPLOYING SELECTIVE DEPOSITION 有权
    无边界联系人选择选择性沉积

    公开(公告)号：US20120126295A1

    公开(公告)日：2012-05-24

    申请号：US12952372

    申请日：2010-11-23

    申请人： Lisa F. Edge ,  Balasubramanian S. Haran

    发明人： Lisa F. Edge ,  Balasubramanian S. Haran

    IPC分类号： H01L21/28 ,  H01L29/78

    CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    摘要： A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided.

    摘要翻译： 可以使用自对准栅极帽电介质来形成与扩散区域的自对准接触，同时防止由于覆盖变化导致的栅极导体的电短路。 在一个实施例中，可电镀或无电镀的金属被选择性地沉积在栅电极中的导电材料上，同时金属不沉积在电介质表面上。 栅极顶部的金属部分被转换成包括金属和氧的栅极电介质。 在另一个实施例中，在电介质表面上形成自组装单层，同时暴露栅电极的金属顶表面。 在未被自组装单层覆盖的区域上形成包括电介质氧化物的栅极电介质。 栅极电介质在形成通孔期间用作蚀刻停止结构，从而避免了在其中形成的接触通孔结构与栅电极之间的电短路。

    METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION
    5.
    发明申请
    METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 有权
    提高生产费用总额的方法

    公开(公告)号：US20110081765A1

    公开(公告)日：2011-04-07

    申请号：US12571483

    申请日：2009-10-01

    申请人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    发明人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76229

    摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

    摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

    Method to improve wet etch budget in FEOL integration
    7.
    发明授权
    Method to improve wet etch budget in FEOL integration 失效
    在FEOL集成中改善湿法蚀刻预算的方法

    公开(公告)号：US08679941B2

    公开(公告)日：2014-03-25

    申请号：US13422138

    申请日：2012-03-16

    申请人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    发明人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229

    摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

    摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

    METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION
    9.
    发明申请
    METHOD TO IMPROVE WET ETCH BUDGET IN FEOL INTEGRATION 失效
    提高生产费用总额的方法

    公开(公告)号：US20120178236A1

    公开(公告)日：2012-07-12

    申请号：US13422138

    申请日：2012-03-16

    申请人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    发明人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76229

    摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

    摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。