Replacement Gate ETSOI with Sharp Junction
    7.
    发明申请
    Replacement Gate ETSOI with Sharp Junction 审中-公开
    更换门ETSOI与夏普结

    公开(公告)号:US20130032876A1

    公开(公告)日:2013-02-07

    申请号:US13195153

    申请日:2011-08-01

    摘要: A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.

    摘要翻译: 晶体管结构包括设置在源极和漏极之间的沟道; 设置在所述通道上并且在所述源极和所述漏极之间的栅极导体; 以及设置在栅极导体和源极之间的栅介质层,漏极和沟道。 在晶体管结构中,源极的下部和与沟道相邻的漏极的下部设置在栅极介电层的下方并与栅极介电层接触以限定明确限定的源 - 漏扩展区。 还公开了制造晶体管结构的替代栅极方法。

    Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions
    9.
    发明授权
    Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions 失效
    具有NFET和PFET的半导体结构形成在具有延伸延伸的SOI衬底中

    公开(公告)号:US08598663B2

    公开(公告)日:2013-12-03

    申请号:US13108290

    申请日:2011-05-16

    摘要: A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

    摘要翻译: 一种半导体结构,其包括绝缘体上半导体(SOI)基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物(BOX)层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路,该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管(NFET)和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管(PFET)和栅极。 每个NFET和PFET下面也可以有一个阱。 存在将非零电偏压施加到SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。