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公开(公告)号：US09135185B2
公开(公告)日：2015-09-15
申请号：US13726143
申请日：2012-12-23
申请人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
发明人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
CPC分类号： G06F12/1027 , H01L25/18 , H01L2224/16225 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.
摘要翻译： 芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。 由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。 由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。
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公开(公告)号：US09170948B2
公开(公告)日：2015-10-27
申请号：US13726146
申请日：2012-12-23
CPC分类号： G06F12/0828 , G11C5/025 , G11C8/12 , G11C29/12 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2225/06541 , H01L2225/06565 , H01L2924/1461 , H01L2924/15311 , Y02D10/13 , H01L2924/00
摘要： A die-stacked memory device implements an integrated coherency manager to offload cache coherency protocol operations for the devices of a processing system. The die-stacked memory device includes a set of one or more stacked memory dies and a set of one or more logic dies. The one or more logic dies implement hardware logic providing a memory interface and the coherency manager. The memory interface operates to perform memory accesses in response to memory access requests from the coherency manager and the one or more external devices. The coherency manager comprises logic to perform coherency operations for shared data stored at the stacked memory dies. Due to the integration of the logic dies and the memory dies, the coherency manager can access shared data stored in the memory dies and perform related coherency operations with higher bandwidth and lower latency and power consumption compared to the external devices.
摘要翻译： 堆叠堆叠的存储器件实现集成的一致性管理器以卸载处理系统的设备的高速缓存一致性协议操作。 芯片堆叠的存储器件包括一组一个或多个堆叠的存储器管芯和一组一个或多个逻辑管芯。 一个或多个逻辑模块实现提供存储器接口和一致性管理器的硬件逻辑。 存储器接口操作以响应来自一致性管理器和一个或多个外部设备的存储器访问请求来执行存储器访问。 相关性管理器包括对存储在堆叠存储器管芯上的共享数据执行一致性操作的逻辑。 由于逻辑管芯和存储器管芯的集成，一致性管理器可以访问存储在存储器管芯中的共享数据，并且与外部器件相比具有更高带宽和更低的延迟和功耗的相关一致性操作。
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3.发明授权公开(公告)号：US09201777B2
公开(公告)日：2015-12-01
申请号：US13726144
申请日：2012-12-23
CPC分类号： G06F12/00 , G06F12/0246 , G06F13/16 , H01L2224/16227 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311
摘要： A die-stacked memory device implements an integrated QoS manager to provide centralized QoS functionality in furtherance of one or more specified QoS objectives for the sharing of the memory resources by other components of the processing system. The die-stacked memory device includes a set of one or more stacked memory dies and one or more logic dies. The logic dies implement hardware logic for a memory controller and the QoS manager. The memory controller is coupleable to one or more devices external to the set of one or more stacked memory dies and operates to service memory access requests from the one or more external devices. The QoS manager comprises logic to perform operations in furtherance of one or more QoS objectives, which may be specified by a user, by an operating system, hypervisor, job management software, or other application being executed, or specified via hardcoded logic or firmware.
摘要翻译： 堆叠堆叠的存储器件实现集成的QoS管理器以提供集中的QoS功能，以促进一个或多个指定的QoS目标，以便由处理系统的其他组件共享存储器资源。 芯片堆叠的存储器件包括一组一个或多个堆叠的存储器管芯和一个或多个逻辑管芯。 逻辑模块为存储器控制器和QoS管理器实现硬件逻辑。 存储器控制器可耦合到一个或多个堆叠的存储器管芯组的外部的一个或多个器件，并且操作以从一个或多个外部器件服务存储器访问请求。 QoS管理器包括用于执行可由操作系统，管理程序，作业管理软件或正在执行的其它应用程序或通过硬编码逻辑或固件指定的一个或多个QoS目标的操作的逻辑。
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公开(公告)号：US20130159812A1
公开(公告)日：2013-06-20
申请号：US13328393
申请日：2011-12-16
申请人： Gabriel H. LOH , James M. O'Connor , Michael Ignatowski , Nuwan S. Jayasena , Bradford M. Beckmann
发明人： Gabriel H. LOH , James M. O'Connor , Michael Ignatowski , Nuwan S. Jayasena , Bradford M. Beckmann
CPC分类号： G11C5/02 , G06F11/1048
摘要： According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data.
摘要翻译： 根据一个实施例，提供了一种存储器架构实现的方法，其中存储器架构包括逻辑芯片和单个管芯上的一个或多个存储器芯片，并且其中该方法包括：从一个或多个存储器芯片读取数据的值 逻辑芯片，其中一个或多个存储器芯片和逻辑芯片在单个芯片上; 通过单个芯片上的逻辑芯片修改数据的值; 并从逻辑芯片向一个或多个存储器芯片写入修改的数据值。
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公开(公告)号：US09697147B2
公开(公告)日：2017-07-04
申请号：US13567945
申请日：2012-08-06
CPC分类号： G06F13/1668 , G06F11/1004 , Y02D10/14
摘要： A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.
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公开(公告)号：US20140040698A1
公开(公告)日：2014-02-06
申请号：US13567945
申请日：2012-08-06
CPC分类号： G06F13/1668 , G06F11/1004 , Y02D10/14
摘要： A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a metadata manager that offloads metadata management from the other system components. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.
摘要翻译： 处理系统包括一个或多个处理器设备和耦合到具有一组堆叠存储器层和一组一个或多个逻辑层的堆叠存储器件的其他系统组件。 逻辑层集合实现了从其他系统组件卸载元数据管理的元数据管理器。 逻辑层集合还包括耦合到存储单元电路的存储器接口，该存储器单元电路被实现在该组堆叠存储器层中，并且可耦合到堆叠存储器件外部的器件。 存储器接口用于对外部设备和元数据管理器执行存储器访问。 由于元数据管理器与堆叠存储器层的紧密集成，元数据管理器可以比由外部设备执行的更有效地执行某些存储器密集型元数据管理操作。
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公开(公告)号：US08621131B2
公开(公告)日：2013-12-31
申请号：US13221465
申请日：2011-08-30
IPC分类号： G06F13/00
CPC分类号： G06F13/4265 , G06F2213/0038
摘要： Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a node of a second semiconductor chip. The packet includes a packet header and packet body. The packet header includes an identification of a first exit point from the first substrate and an identification of the node. The packet is sent to the first substrate and eventually to the node of the second semiconductor chip.
摘要翻译： 公开了各种方法，计算机可读介质，制品和系统。 一方面，提供一种包括用第一半导体芯片产生分组的方法。 分组旨在传送第一衬底并由第二半导体芯片的节点接收。 分组包括分组报头和分组主体。 分组报头包括来自第一基板的第一出口点的标识和节点的标识。 分组被发送到第一衬底并且最终传送到第二半导体芯片的节点。
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公开(公告)号：US20130054849A1
公开(公告)日：2013-02-28
申请号：US13221465
申请日：2011-08-30
IPC分类号： G06F13/00
CPC分类号： G06F13/4265 , G06F2213/0038
摘要： Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a node of a second semiconductor chip. The packet includes a packet header and packet body. The packet header includes an identification of a first exit point from the first substrate and an identification of the node. The packet is sent to the first substrate and eventually to the node of the second semiconductor chip.
摘要翻译： 公开了各种方法，计算机可读介质，制品和系统。 一方面，提供一种包括用第一半导体芯片产生分组的方法。 分组旨在传送第一衬底并由第二半导体芯片的节点接收。 分组包括分组报头和分组主体。 分组报头包括来自第一基板的第一出口点的标识和节点的标识。 分组被发送到第一衬底并且最终传送到第二半导体芯片的节点。
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公开(公告)号：US09342334B2
公开(公告)日：2016-05-17
申请号：US13530793
申请日：2012-06-22
CPC分类号： G06F9/4552 , G06F11/3644 , G06F17/5022 , G06F2217/86
摘要： A system and method for simulating new instructions without compiler support for the new instructions. A simulator detects a given region in code generated by a compiler. The given region may be a candidate for vectorization or may be a region already vectorized. In response to the detection, the simulator suspends execution of a time-based simulation. The simulator then serially executes the region for at least two iterations using a functional-based simulation and using instructions with operands which correspond to P or less lanes of single-instruction-multiple-data (SIMD) execution. The value P is a maximum number of lanes of SIMD exection supported both by the compiler. The simulator stores checkpoint state during the serial execution. In response to determining no inter-iteration memory dependencies exist, the simulator returns to the time-based simulation and resumes execution using N-wide vector instructions.
摘要翻译： 用于模拟新指令的系统和方法，无需编译器支持新指令。 模拟器会检测编译器生成的代码中的给定区域。 给定区域可以是向量化的候选者，或者可以是已经向量化的区域。 响应于该检测，模拟器暂停执行基于时间的模拟。 仿真器然后使用基于功能的仿真并使用具有对应于单指令多数据（SIMD）执行的P或更少通道的操作数的指令来串行地执行该区域至少两次迭代。 值P是由编译器支持的SIMD exection的最大通道数。 模拟器在串行执行期间存储检查点状态。 响应于确定不存在迭代存储器依赖性，仿真器返回到基于时间的仿真，并使用N宽向量指令恢复执行。
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公开(公告)号：US20130346058A1
公开(公告)日：2013-12-26
申请号：US13530793
申请日：2012-06-22
IPC分类号： G06F9/45
CPC分类号： G06F9/4552 , G06F11/3644 , G06F17/5022 , G06F2217/86
摘要： A system and method for simulating new instructions without compiler support for the new instructions. A simulator detects a given region in code generated by a compiler. The given region may be a candidate for vectorization or may be a region already vectorized. In response to the detection, the simulator suspends execution of a time-based simulation. The simulator then serially executes the region for at least two iterations using a functional-based simulation and using instructions with operands which correspond to P or less lanes of single-instruction-multiple-data (SIMD) execution. The value P is a maximum number of lanes of SIMD exection supported both by the compiler. The simulator stores checkpoint state during the serial execution. In response to determining no inter-iteration memory dependencies exist, the simulator returns to the time-based simulation and resumes execution using N-wide vector instructions.
摘要翻译： 用于模拟新指令的系统和方法，无需编译器支持新指令。 模拟器会检测编译器生成的代码中的给定区域。 给定区域可以是向量化的候选者，或者可以是已经向量化的区域。 响应于该检测，模拟器暂停执行基于时间的模拟。 仿真器然后使用基于功能的仿真并使用具有对应于单指令多数据（SIMD）执行的P或更少通道的操作数的指令来串行地执行该区域至少两次迭代。 值P是由编译器支持的SIMD exection的最大通道数。 模拟器在串行执行期间存储检查点状态。 响应于确定不存在迭代存储器依赖性，仿真器返回到基于时间的仿真，并使用N宽向量指令恢复执行。
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