公开(公告)号：US07087997B2

公开(公告)日：2006-08-08

申请号：US09805027

申请日：2001-03-12

申请人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

发明人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

公开(公告)号：US07037824B2

公开(公告)日：2006-05-02

申请号：US10844533

申请日：2004-05-13

申请人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

发明人： Lloyd G. Burrell ,  Edward E. Cooney, III ,  Jeffrey P. Gambino ,  John E. Heidenreich, III ,  Hyun Koo Lee ,  Mark D. Levy ,  Baozhen Li ,  Stephen E. Luce ,  Thomas L. McDevitt ,  Anthony K. Stamper ,  Kwong Hon Wong ,  Sally J. Yankee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

公开(公告)号：US06383929B1

公开(公告)日：2002-05-07

申请号：US09759015

申请日：2001-01-11

申请人： Steven H. Boettcher ,  Herbert L. Ho ,  Mark Hoinkis ,  Hyun Koo Lee ,  Yun-Yu Wang ,  Kwong Hon Wong

发明人： Steven H. Boettcher ,  Herbert L. Ho ,  Mark Hoinkis ,  Hyun Koo Lee ,  Yun-Yu Wang ,  Kwong Hon Wong

IPC分类号： H01L2144

CPC分类号： H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

摘要翻译： 在具有铜互连和低k层间电介质的集成电路中，通过使用第一内衬层Ti，随后是CVD TiN的共形内衬层，然后依次由 Ta或TaN的最终衬垫层，从而改善了通孔和下面的铜层之间的粘附性，同时将Ti和铜之间的合金化引起的电阻增加减少到可接受的量。

公开(公告)号：US06504207B1

公开(公告)日：2003-01-07

申请号：US09609292

申请日：2000-06-30

申请人： Bomy A. Chen ,  Jay G. Harrington ,  Kevin M. Houlihan ,  Dennis Hoyniak ,  Chung Hon Lam ,  Hyun Koo Lee ,  Rebecca D. Mih ,  Jed H. Rankin

发明人： Bomy A. Chen ,  Jay G. Harrington ,  Kevin M. Houlihan ,  Dennis Hoyniak ,  Chung Hon Lam ,  Hyun Koo Lee ,  Rebecca D. Mih ,  Jed H. Rankin

IPC分类号： H01L2976

CPC分类号： H01L21/28273 ,  G11C16/0408 ,  H01L29/42328

摘要： A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.

摘要翻译： 与高性能逻辑或NVRAM集成的EEPROM存储器件的方法和结构。 EEPROM器件包括浮置栅极和彼此自对准的程序栅极。 在编程期间，在浮栅和程序门之间发生电子隧穿。

公开(公告)号：US5731246A

公开(公告)日：1998-03-24

申请号：US730168

申请日：1996-10-15

申请人： Paul Evans Bakeman, Jr. ,  Hyun Koo Lee ,  Stephen Ellinwood Luce

发明人： Paul Evans Bakeman, Jr. ,  Hyun Koo Lee ,  Stephen Ellinwood Luce

IPC分类号： G03F7/11 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/469

CPC分类号： H01L21/02071 ,  G03F7/11 ,  H01L21/321 ,  Y10S148/015 ,  Y10S438/958

摘要： A conductive layer in a semiconductor device is protected against chemical attack by a photoresist developer by forming a protective film overlying the conductive layer. The protective film is formed using a chemical reaction that occurs through defects in a passivation layer that was previously formed overlying the conductive layer. The chemical reaction substantially occurs at the surface of the conductive layer and chemically converts portions thereof in forming the protective film. Preferably, the conductive layer is aluminum or an alloy thereof containing copper and/or silicon, and the protective film is aluminum oxide formed on the aluminum layer to protect it from corrosion by tetramethyl ammonium hydroxide (TMAH). The passivation layer is TiN, and the chemical reaction used is oxidation of the aluminum layer through defects in the overlying TiN layer by placing in an ozone asher.