公开(公告)号：US20240178134A1

公开(公告)日：2024-05-30

申请号：US18437549

申请日：2024-02-09

Applicant: Lodestar Licensing Group LLC

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay ,  Jeffrey D. Runia ,  Matthew Holland ,  Chamunda N. Chamunda

IPC: H01L23/522 ,  G11C7/18 ,  G11C8/14 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure, a stadium structure within the stack structure, and conductive contact structures. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each of the tiers comprises one of the conductive structures and one of the insulative structures. The stadium structure comprises a forward staircase structure having steps comprising edges of the tiers, and a reverse staircase structure opposing the forward staircase structure and having additional steps comprising additional edges of the tiers. The conductive contact structures vertically extend to upper vertical boundaries of at least some of the conductive structures of the stack structure at the steps of the forward staircase structure and the additional steps of the reverse staircase structure, and are each integral and continuous with one of the conductive structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20250071996A1

公开(公告)日：2025-02-27

申请号：US18944590

申请日：2024-11-12

Applicant: Lodestar Licensing Group, LLC

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H10B43/27 ,  G11C16/04 ,  H01L21/02 ,  H01L21/67 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B51/20

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US12167599B2

公开(公告)日：2024-12-10

申请号：US18083991

申请日：2022-12-19

Applicant: Lodestar Licensing Group, LLC

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H10B43/27 ,  G11C16/04 ,  H01L21/02 ,  H01L21/67 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B51/20

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20240357820A1

公开(公告)日：2024-10-24

申请号：US18762200

申请日：2024-07-02

Applicant: Lodestar Licensing Group LLC

Inventor： S M Istiaque Hossain ,  Tom J. John ,  Darwin A. Clampitt ,  Anilkumar Chandolu ,  Parkash Rau Mokhna Rau ,  Christopher J. Larsen ,  Kye Hyun Baek

IPC: H10B43/27 ,  H01L21/768

CPC classification number: H10B43/27 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.