公开(公告)号：US20050124124A1

公开(公告)日：2005-06-09

申请号：US10995677

申请日：2004-11-23

申请人： Jurgen Amon ,  Jurgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Muller ,  Dirk Offenberg ,  Thomas Schuster

发明人： Jurgen Amon ,  Jurgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Muller ,  Dirk Offenberg ,  Thomas Schuster

IPC分类号： H01L27/108 ,  H01L21/265 ,  H01L21/8242 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10888

摘要： A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

摘要翻译： 一种制造半导体结构的方法，该半导体结构具有设置在第一导电类型的半导体衬底中的多个存储单元，并且包含多个平面选择晶体管和与其连接的对应的多个存储电容器。 选择晶体管具有第二导电类型的相应的第一和第二有源区。 第一有源区连接到存储电容器，并且第二有源区连接到以栅极电介质绝缘的方式设置在半导体衬底之上的相应位线和相应的栅极堆叠。 在这种情况下，实现单面晕圈掺杂，并且通过引入扩散抑制物质来防止晕圈掺杂区的过度扩散。

公开(公告)号：US07259060B2

公开(公告)日：2007-08-21

申请号：US10995677

申请日：2004-11-23

申请人： Jürgen Amon ,  Jürgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Müller ,  Dirk Offenberg ,  Thomas Schuster

发明人： Jürgen Amon ,  Jürgen Faul ,  Johann Alsmeier ,  Matthias Goldbach ,  Albrecht Kieslich ,  Ralf Müller ,  Dirk Offenberg ,  Thomas Schuster

IPC分类号： H01L21/8242

CPC分类号： H01L21/26586 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10888

摘要： A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

摘要翻译： 一种制造半导体结构的方法，该半导体结构具有设置在第一导电类型的半导体衬底中的多个存储单元，并且包含多个平面选择晶体管和与其连接的对应的多个存储电容器。 选择晶体管具有第二导电类型的相应的第一和第二有源区。 第一有源区连接到存储电容器，并且第二有源区连接到以栅极电介质绝缘的方式设置在半导体衬底之上的相应位线和相应的栅极堆叠。 在这种情况下，实现单面晕圈掺杂，并且通过引入扩散抑制物质来防止晕圈掺杂区的过度扩散。

公开(公告)号：US07235447B2

公开(公告)日：2007-06-26

申请号：US11035705

申请日：2005-01-14

申请人： Ulrich Frey ,  Matthias Goldbach ,  Dirk Offenberg

发明人： Ulrich Frey ,  Matthias Goldbach ,  Dirk Offenberg

IPC分类号： H01L21/8234

CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/6656

摘要： The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps:provision of a semiconductor substrate (1) with a gate dielectric (5); provision of a plurality of multilayered, elongate gate stacks (GS1; GS2) which essentially run parallel to one another on the gate dielectric (5), which gate stacks have a bottommost layer (10) made of silicon; provision of a first liner layer (60) made of a first material over the gate stacks (GS1; GS2) and the gate dielectric (5) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h′) of the bottommost layer (10) made of silicon; provision of sidewall spacers (70) made of a second material on the vertical sidewalls of the gate stacks (GS1; GS2) over the first liner layer (60), a region of the first liner layer (60) over the gate dielectric (5) between the gate stacks (GS1; GS2) remaining free; selective removal of the first liner layer (60) with respect to the sidewall spacers (70) for the purpose of laterally uncovering the bottommost layer (10) made of silicon of the gate stacks (GS1; GS2); and selective oxidation of the uncovered bottommost layer (10) for the purpose of forming sidewall oxide regions (50′) on the gate stacks (GS1; GS2).

摘要翻译： 本发明提供一种用于半导体结构和相应的半导体结构的制造方法。 制造方法包括以下步骤：提供具有栅极电介质（5）的半导体衬底（1）; 提供多个多层细长的栅极叠层（GS1; GS2），其基本上在栅极电介质（5）上彼此平行地延伸，该栅极堆叠具有由硅制成的最底层（10）; 提供由栅极叠层（GS1; GS2）和栅极电介质（5）制成的由第一材料制成的第一衬垫层（60）未被覆盖在其后面，衬垫层的厚度（h）小于 由硅制成的最下层（10）的厚度（h'）; 在第一衬垫层（60）上设置由栅极堆叠（GS1; GS2）的垂直侧壁上的由第二材料制成的侧壁间隔物（70），第一衬里层（60）的位于栅极电介质 （5）在栅极堆栈（GS 1; GS 2）之间保持自由; 为了横向露出由栅极堆叠（GS1; GS2）的硅制成的最底层（10）的目的，相对于侧壁间隔物（70）选择性地去除第一衬里层（60） 以及为了在栅极堆叠（GS1; GS2）上形成侧壁氧化物区域（50'），未覆盖的最底层（10）的选择性氧化。

公开(公告)号：US20050173729A1

公开(公告)日：2005-08-11

申请号：US11035705

申请日：2005-01-14

申请人： Ulrich Frey ,  Matthias Goldbach ,  Dirk Offenberg

发明人： Ulrich Frey ,  Matthias Goldbach ,  Dirk Offenberg

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L27/085 ,  H01L27/105 ,  H01L29/49 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/6656

摘要： The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps: provision of a semiconductor substrate (1) with a gate dielectric (5); provision of a plurality of multilayered, elongate gate stacks (GS1; GS2) which essentially run parallel to one another on the gate dielectric (5), which gate stacks have a bottommost layer (10) made of silicon; provision of a first liner layer (60) made of a first material over the gate stacks (GS1; GS2) and the gate dielectric (5) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h′) of the bottommost layer (10) made of silicon; provision of sidewall spacers (70) made of a second material on the vertical sidewalls of the gate stacks (GS1; GS2) over the first liner layer (60), a region of the first liner layer (60) over the gate dielectric (5) between the gate stacks (GS1; GS2) remaining free; selective removal of the first liner layer (60) with respect to the sidewall spacers (70) for the purpose of laterally uncovering the bottommost layer (10) made of silicon of the gate stacks (GS1; GS2); and selective oxidation of the uncovered bottommost layer (10) for the purpose of forming sidewall oxide regions (50′) on the gate stacks (GS1; GS2).

摘要翻译： 本发明提供一种用于半导体结构和相应的半导体结构的制造方法。 制造方法包括以下步骤：提供具有栅极电介质（5）的半导体衬底（1）; 提供多个多层细长的栅极叠层（GS1; GS2），其基本上在栅极电介质（5）上彼此平行地延伸，该栅极堆叠具有由硅制成的最底层（10）; 提供由栅极叠层（GS1; GS2）和栅极电介质（5）制成的由第一材料制成的第一衬垫层（60）未被覆盖在其后面，衬垫层的厚度（h）小于 由硅制成的最下层（10）的厚度（h'）; 在第一衬垫层（60）上设置由栅极堆叠（GS1; GS2）的垂直侧壁上的由第二材料制成的侧壁间隔物（70），第一衬里层（60）的位于栅极电介质 （5）在栅极堆栈（GS 1; GS 2）之间保持自由; 为了横向露出由栅极堆叠（GS1; GS2）的硅制成的最底层（10）的目的，相对于侧壁间隔物（70）选择性地去除第一衬里层（60） 以及为了在栅极堆叠（GS1; GS2）上形成侧壁氧化物区域（50'），未覆盖的最底层（10）的选择性氧化。

公开(公告)号：US07220664B2

公开(公告)日：2007-05-22

申请号：US11061731

申请日：2005-02-22

申请人： Stephan Hartmann ,  Dirk Offenberg ,  Mirko Vogt

发明人： Stephan Hartmann ,  Dirk Offenberg ,  Mirko Vogt

IPC分类号： H01L21/4763

CPC分类号： H01L27/10888 ,  H01L21/76802 ,  H01L21/7682

摘要： The present invention provides a fabrication method for a semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently. A fabrication of a patterned first region in the substrate, so that the semiconductor structure has a non-patterned second region and the patterned first region, is followed by a deposition of a cover layer that grows over the patterned first region, so that the cover layer above the patterned first region forms a closure, which covers over the patterned first region. This is followed by a fabrication of the patterned second region, the patterned first region remaining protected at least by the closure of the cover layer. The final step effected is a removal of the cover layer above the semiconductor structure, which now has two differently patterned regions.

摘要翻译： 本发明提供了一种用于衬底中的半导体结构的制造方法，该半导体结构具有至少两个待图案化的区域。 在衬底中制造图案化的第一区域，使得半导体结构具有非图案化的第二区域和图案化的第一区域，随后沉积在图案化的第一区域上生长的覆盖层，使得覆盖物 在图案化的第一区域之上的层形成封闭物，覆盖在图案化的第一区域上。 之后是图案化的第二区域的制造，图案化的第一区域至少被覆盖层的封闭保护。 实现的最后一步是去除半导体结构上方的覆盖层，其现在具有两个不同图案的区域。

公开(公告)号：US20070090531A1

公开(公告)日：2007-04-26

申请号：US11246916

申请日：2005-10-07

申请人： Dirk Offenberg ,  Mirko Vogt ,  Hans-Peter Sperlich ,  Jean Cigal

发明人： Dirk Offenberg ,  Mirko Vogt ,  Hans-Peter Sperlich ,  Jean Cigal

IPC分类号： H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/7682 ,  C23C16/26 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/31633 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).

公开(公告)号：US07115501B2

公开(公告)日：2006-10-03

申请号：US10937903

申请日：2004-09-10

申请人： Uwe Kahler ,  Dirk Offenberg

发明人： Uwe Kahler ,  Dirk Offenberg

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877

摘要： A method for fabricating an integrated circuit device, an electrically conductive substrate being provided, an insulation layer being deposited on the substrate, the insulation layer being etched in structures, a contact-making layer being deposited on the patterned insulation layer and on the substrate in depressions which have first and second lateral dimensions, the contact-making layer being etched back in such a way that the contact-making layer is preserved in the structures with the depressions which have first lateral dimensions of the order of magnitude of the structure depth of the insulation layer and the contact-making layer is removed in the structures with depressions which have second lateral dimensions significantly greater than the structure depth of the insulation layer.

摘要翻译： 一种制造集成电路器件的方法，提供导电衬底，绝缘层沉积在衬底上，绝缘层在结构上被蚀刻，接触层沉积在图案化的绝缘层上和衬底上 凹陷具有第一和第二横向尺寸，接触层被回蚀，使接触层保留在具有第一横向尺寸为结构深度的数量级的凹陷的结构中 在具有凹陷的结构中去除绝缘层和接触层，所述凹陷具有明显大于绝缘层的结构深度的第二横向尺寸。

公开(公告)号：US20070059892A1

公开(公告)日：2007-03-15

申请号：US11513835

申请日：2006-08-31

申请人： Matthias Kroenke ,  Dirk Offenberg

发明人： Matthias Kroenke ,  Dirk Offenberg

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L27/10873 ,  H01L27/10894

摘要： A semiconductor structure is fabricated to have a transistor cell region and a connection region. The transistors both of a transistor cell region and of a connection region are coated with a first oxide layer, the layer thickness of the first oxide layer being dimensioned in such a way that a gap region in each case remains present between the adjacent transistors in the transistor cell region. A sacrificial structure is subsequently applied between at least two adjacent transistors of the transistor cell region in the gap region. At least one gap region in each case remains free between two adjacent sacrificial structures. A second oxide layer is applied to the sacrificial structures and the first oxide layer. The first and second oxide layers are subjected to an etching step in which at least one spacer having a predetermined spacer width is formed on the side edges of at least one transistor of the connection region, the spacer being formed by the first and second oxide layers and the spacer width being determined by the layer thickness of the first and second oxide layers and also by the etching step.

摘要翻译： 制造半导体结构以具有晶体管单元区域和连接区域。 晶体管单元区域和连接区域的晶体管都涂覆有第一氧化物层，第一氧化物层的层厚度的尺寸使得每种情况下的间隙区域保持在相邻晶体管之间的间隙区域中 晶体管单元区域。 随后在间隙区域中的晶体管单元区域的至少两个相邻晶体管之间施加牺牲结构。 在每种情况下，至少一个间隙区域在两个相邻的牺牲结构之间保持自由。 第二氧化物层被施加到牺牲结构和第一氧化物层。 对第一氧化物层和第二氧化物层进行蚀刻步骤，其中在连接区域的至少一个晶体管的侧边缘上形成具有预定间隔物宽度的至少一个间隔物，间隔物由第一和第二氧化物层形成 并且间隔物宽度由第一和第二氧化物层的层厚度以及蚀刻步骤决定。

公开(公告)号：US20050073046A1

公开(公告)日：2005-04-07

申请号：US10937903

申请日：2004-09-10

申请人： Uwe Kahler ,  Dirk Offenberg

发明人： Uwe Kahler ,  Dirk Offenberg

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L29/40

CPC分类号： H01L21/76877

摘要： A method for fabricating an integrated circuit device, an electrically conductive substrate being provided, an insulation layer being deposited on the substrate, the insulation layer being etched in structures, a contact-making layer being deposited on the patterned insulation layer and on the substrate in depressions which have first and second lateral dimensions, the contact-making layer being etched back in such a way that the contact-making layer is preserved in the structures with the depressions which have first lateral dimensions of the order of magnitude of the structure depth of the insulation layer and the contact-making layer is removed in the structures with depressions which have second lateral dimensions significantly greater than the structure depth of the insulation layer.

摘要翻译： 一种制造集成电路器件的方法，提供导电衬底，绝缘层沉积在衬底上，绝缘层在结构上被蚀刻，接触层沉积在图案化的绝缘层上和衬底上 凹陷具有第一和第二横向尺寸，接触层被回蚀，使接触层保留在具有第一横向尺寸为结构深度的数量级的凹陷的结构中 在具有凹陷的结构中去除绝缘层和接触层，所述凹陷具有明显大于绝缘层的结构深度的第二横向尺寸。

公开(公告)号：US20070264819A1

公开(公告)日：2007-11-15

申请号：US11280802

申请日：2005-11-16

申请人： Dirk Offenberg ,  Mirko Vogt ,  Hans-Peter Sperlich ,  Jean Cigal

发明人： Dirk Offenberg ,  Mirko Vogt ,  Hans-Peter Sperlich ,  Jean Cigal

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a wiring level and an electrical isolation associated with the wiring level on a surface of a semiconductor wafer comprises the steps of providing the semiconductor wafer having said surface, forming a plurality of electrically conductive wiring lines upon said surface, each of the wiring lines having a spacing with respect to neighboring one of the wiring lines, depositing a first layer of amorphous carbon upon the wiring lines by means of non-conformal plasma enhanced chemical vapor deposition (PECVD), such that air-filled voids formed below the first layer within the spacings between neighboring wiring lines. Alternatively, OSG (organo-silicon glass) or FSG (fluorine doped silicon glass) may be deposited to yield air-filled voids within the spacings. According to an embodiment, the carbon, OSG or FSG layers are used as an IMD-layer (line-to-line isolation), added by a further layer of a dielectric material, which then serves as an ILD-layer (level-to-level isolation).

摘要翻译： 形成与半导体晶片的表面上的配线水平相关联的配线水平和电隔离的方法包括以下步骤：提供具有所述表面的半导体晶片，在所述表面上形成多个导电布线， 布线相对于相邻的一条布线具有间隔，通过非共形等离子体增强化学气相沉积（PECVD）在布线上沉积第一层无定形碳，使得形成在下面的空气填充的空隙 第一层在相邻布线之间的间隔内。 或者，可以沉积OSG（有机硅玻璃）或FSG（氟掺杂硅玻璃）以在间隔内产生空气填充的空隙。 根据一个实施方案，碳，OSG或FSG层用作IMD层（线对线隔离），由另外的介电材料层加入，其然后用作ILD层（水平到 级隔离）。