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    THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION
    5.
    发明申请
    THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION 有权
    三维芯片堆叠同步

    公开(公告)号：US20100277210A1

    公开(公告)日：2010-11-04

    申请号：US12432801

    申请日：2009-04-30

    申请人： Ping-Chuan Wang ,  Anthony R. Bonaccio ,  Jong-Ru Guo ,  Louis Lu-Chen Hsu

    发明人： Ping-Chuan Wang ,  Anthony R. Bonaccio ,  Jong-Ru Guo ,  Louis Lu-Chen Hsu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/099 ,  H03L7/18 ,  H03L7/22

    摘要： a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.

    摘要翻译： 中心参考时钟被放置在3-D芯片堆叠的基本上中间的芯片中。 中心参考时钟被分配给3-D芯片组的每个子芯片，从而以同步的方式为3-D堆叠中的每个芯片生成多个时钟。 采用预定数量的通硅通孔和片上导线来形成每个从时钟的延迟元件，确保为每个子芯片生成的时钟基本上同步。 可选地，嵌入式片上时钟微调电路用于进一步精确调谐以消除本地时钟偏移。

    Three-dimensional chip-stack synchronization
    7.
    发明授权
    Three-dimensional chip-stack synchronization 有权
    三维芯片堆栈同步

    公开(公告)号：US07863960B2

    公开(公告)日：2011-01-04

    申请号：US12432801

    申请日：2009-04-30

    申请人： Ping-Chuan Wang ,  Anthony R. Bonaccio ,  Jong-Ru Guo ,  Louis Lu-Chen Hsu

    发明人： Ping-Chuan Wang ,  Anthony R. Bonaccio ,  Jong-Ru Guo ,  Louis Lu-Chen Hsu

    IPC分类号： G06F1/04

    CPC分类号： H03L7/099 ,  H03L7/18 ,  H03L7/22

    摘要： A central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.

    摘要翻译： 中心参考时钟被放置在3-D芯片堆叠的基本上中间的芯片中。 中心参考时钟被分配给3-D芯片组的每个子芯片，从而以同步的方式为3-D堆叠中的每个芯片生成多个时钟。 采用预定数量的通硅通孔和片上导线来形成每个从时钟的延迟元件，确保为每个子芯片生成的时钟基本上同步。 可选地，嵌入式片上时钟微调电路用于进一步精确调谐以消除本地时钟偏移。

    Leakage Current Mitigation in a Semiconductor Device
    9.
    发明申请
    Leakage Current Mitigation in a Semiconductor Device 有权
    半导体器件漏电流减轻

    公开(公告)号：US20100327958A1

    公开(公告)日：2010-12-30

    申请号：US12494460

    申请日：2009-06-30

    申请人： Jong-Ru Guo ,  Louis Lu-Chen Hsu ,  Rajiv Vasant Joshi ,  Ping-Chuan Wang ,  Zhijian Yang

    发明人： Jong-Ru Guo ,  Louis Lu-Chen Hsu ,  Rajiv Vasant Joshi ,  Ping-Chuan Wang ,  Zhijian Yang

    IPC分类号： H03K3/01 ,  G01R31/26

    CPC分类号： H03K17/0822

    摘要： A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal switches the target semiconductor device to an active mode for leakage mitigation, which includes a repair voltage from a repair voltage generator applied to the gate of the target semiconductor device.

    摘要翻译： 识别泄漏电流目标单元内的休眠模式目标半导体器件，以减轻漏电流，防止其达到灾难性的失控。 泄漏电流移动监视器单元电连接到泄漏电流目标单元的输出节点，并在两个连续的预定义时间周期内从所选择的目标半导体器件收集泄漏电流，并测量所收集的漏电流之间的差异。 比较器接收并比较当前移位监视器单元和参考电压发生器的输出。 当从泄漏电流移动监视器单元输出的泄漏电压超过参考电压时，比较器将报警信号传播到泄漏电流目标单元，表示泄漏电流即将接近灾难性失控水平的条件。 该警报信号将目标半导体器件切换到用于泄漏减轻的活动模式，其包括施加到目标半导体器件的栅极的修复​​电压发生器的修复电压。