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公开(公告)号：US20100176506A1
公开(公告)日：2010-07-15
申请号：US12351878
申请日：2009-01-12
申请人： Louis Lu-Chen Hsu , Ping-Chuan Wang , Xiaojin Wei , Huilong Zhu
发明人： Louis Lu-Chen Hsu , Ping-Chuan Wang , Xiaojin Wei , Huilong Zhu
IPC分类号： H01L23/36 , H01L21/3205
CPC分类号： H01L23/481 , H01L25/0657 , H01L27/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , Y10S257/93 , H01L2924/00
摘要： The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.
摘要翻译： 本发明包括具有中间热电耦合（TEC）板的3D芯片堆叠。 通过3D芯片堆叠中的硅通孔在3D堆叠中的芯片之间传送电子信号，为TEC板供电，以及将堆叠中的热量从较热的芯片分配到较冷的芯片。
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公开(公告)号：US08030113B2
公开(公告)日：2011-10-04
申请号：US12985360
申请日：2011-01-06
申请人： Louis Lu-Chen Hsu , Ping-Chuan Wang , Xiaojin Wei , Huilong Zhu
发明人： Louis Lu-Chen Hsu , Ping-Chuan Wang , Xiaojin Wei , Huilong Zhu
CPC分类号： H01L23/481 , H01L25/0657 , H01L27/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , Y10S257/93 , H01L2924/00
摘要： The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.
摘要翻译： 本发明包括具有中间热电耦合（TEC）板的3D芯片堆叠。 通过3D芯片堆叠中的硅通孔在3D堆叠中的芯片之间传送电子信号，为TEC板供电，以及将堆叠中的热量从较热的芯片分配到较冷的芯片。
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公开(公告)号：US07893529B2
公开(公告)日：2011-02-22
申请号：US12351878
申请日：2009-01-12
申请人： Louis Lu-Chen Hsu , Ping-Chuan Wang , Xiaojin Wei , Huilong Zhu
发明人： Louis Lu-Chen Hsu , Ping-Chuan Wang , Xiaojin Wei , Huilong Zhu
CPC分类号： H01L23/481 , H01L25/0657 , H01L27/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , Y10S257/93 , H01L2924/00
摘要： The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.
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公开(公告)号：US20110104846A1
公开(公告)日：2011-05-05
申请号：US12985360
申请日：2011-01-06
申请人： Louis Lu-Chen Hsu , Ping-Chuan Wang , Xiaojin Wei , Huilong Zhu
发明人： Louis Lu-Chen Hsu , Ping-Chuan Wang , Xiaojin Wei , Huilong Zhu
IPC分类号： H01L21/71
CPC分类号： H01L23/481 , H01L25/0657 , H01L27/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , Y10S257/93 , H01L2924/00
摘要： The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.
摘要翻译： 本发明包括具有中间热电耦合（TEC）板的3D芯片堆叠。 通过3D芯片堆叠中的硅通孔在3D堆叠中的芯片之间传送电子信号，为TEC板供电，以及将堆叠中的热量从较热的芯片分配到较冷的芯片。
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公开(公告)号：US20110102005A1
公开(公告)日：2011-05-05
申请号：US12610683
申请日：2009-11-02
IPC分类号： G01R31/26 , G01R31/3187
CPC分类号： G01R31/2856 , G01R31/2875
摘要： An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.
摘要翻译： 嵌入在半导体芯片上的加速故障指示器包括绝缘区域; 位于绝缘区域内的电路; 位于所述绝缘区域内的加热元件，所述加热元件构造成将所述电路加热至高于所述半导体芯片的工作温度的温度; 以及可靠性监视器，其被配置为监视所述电路的劣化，并且还被配置为在所述电路的劣化超过预定阈值的情况下触发警报。 一种操作嵌入在半导体芯片上的加速故障指示器的方法包括确定半导体芯片的工作温度; 将位于加速故障指示器的绝缘区域内的电路加热到高于所确定的工作温度的温度; 监控电路退化; 并且在电路的劣化超过预定阈值的情况下触发报警。
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公开(公告)号：US08274301B2
公开(公告)日：2012-09-25
申请号：US12610683
申请日：2009-11-02
CPC分类号： G01R31/2856 , G01R31/2875
摘要： An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.
摘要翻译： 嵌入在半导体芯片上的加速故障指示器包括绝缘区域; 位于绝缘区域内的电路; 位于所述绝缘区域内的加热元件，所述加热元件构造成将所述电路加热至高于所述半导体芯片的工作温度的温度; 以及可靠性监视器，其被配置为监视所述电路的劣化，并且还被配置为在所述电路的劣化超过预定阈值的情况下触发警报。 一种操作嵌入在半导体芯片上的加速故障指示器的方法包括确定半导体芯片的工作温度; 将位于加速故障指示器的绝缘区域内的电路加热到高于所确定的工作温度的温度; 监控电路退化; 并且在电路的劣化超过预定阈值的情况下触发报警。
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7.发明授权Semiconductor package structures having liquid coolers integrated with first level chip package modules 有权具有与第一级芯片封装模块集成的液体冷却器的半导体封装结构公开(公告)号：US08115303B2
公开(公告)日：2012-02-14
申请号：US12120029
申请日：2008-05-13
申请人： Raschid Jose Bezama , Evan George Colgan , Michael Gaynes , John Harold Magerlein , Kenneth C. Marston , Xiaojin Wei
发明人： Raschid Jose Bezama , Evan George Colgan , Michael Gaynes , John Harold Magerlein , Kenneth C. Marston , Xiaojin Wei
IPC分类号： H01L23/40
CPC分类号： H01L23/473 , H01L23/3675 , H01L23/49833 , H01L23/4985 , H01L2023/4043 , H01L2023/4087 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/10253 , H01L2924/15311 , H01L2924/19105 , H01L2924/00
摘要： Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.
摘要翻译： 提供半导体封装结构，其被设计成具有与第一级芯片模块整体封装的液体冷却器。 特别地，用于将第一级芯片封装结构中的液体冷却器装置整体封装的装置包括其中液体冷却器装置直接热耦合到安装在柔性芯片载体衬底上的集成电路芯片倒装芯片的背面的结构。 液体冷却器装置通过金属加强结构机械耦合到封装基板，金属加强结构结合到柔性封装基板上，以向柔性封装基板提供机械刚性。
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8.发明授权Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging 有权通过偏移来减少微电子封装中第一级互连（FLI）下的应力公开(公告)号：US07812438B2
公开(公告)日：2010-10-12
申请号：US11970130
申请日：2008-01-07
IPC分类号： H01L23/04
CPC分类号： H01L24/12 , H01L2224/05572 , H01L2224/05573 , H01L2224/056 , H01L2224/13099 , H01L2224/141 , H01L2224/14104 , H01L2224/16 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip.
摘要翻译： 本发明涉及一种改进的微电子器件，其通过减小施加在通孔上的拉应力来降低BEOL分层，所述通孔将第一级互连与BEOL连接。 通过将通孔移向硅芯片的中心或者将UBM转移到硅芯片的角部来减小施加在通孔上的拉伸应力。
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公开(公告)号：US07759789B2
公开(公告)日：2010-07-20
申请号：US12013653
申请日：2008-01-14
申请人： Kai Di Feng , Alvin Jose Joseph , Donald J. Papae , Xiaojin Wei
发明人： Kai Di Feng , Alvin Jose Joseph , Donald J. Papae , Xiaojin Wei
CPC分类号： H01L23/3677 , H01L23/38 , H01L24/48 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2224/73253 , H01L2924/00014 , H01L2924/12041 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.
摘要翻译： 一种系统和方法，其中半导体芯片具有与半导体器件或待冷却的器件相邻的电惰性金属填充的通孔，并且半导体器件或器件优选地被隔热通孔包围。 金属填充的通孔与热电冷却器接触以从半导体器件或器件去除多余的热量。
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10.发明授权Semiconductor package structures having liquid cooler integrated with first level chip package modules 有权具有与第一级芯片封装模块集成的液体冷却器的半导体封装结构公开(公告)号：US08772927B2
公开(公告)日：2014-07-08
申请号：US13290824
申请日：2011-11-07
申请人： Raschid Jose Bezama , Evan George Colgan , Michael Gaynes , John Harold Magerlein , Kenneth C. Marston , Xiaojin Wei
发明人： Raschid Jose Bezama , Evan George Colgan , Michael Gaynes , John Harold Magerlein , Kenneth C. Marston , Xiaojin Wei
IPC分类号： H01L23/34
CPC分类号： H01L23/473 , H01L23/3675 , H01L23/49833 , H01L23/4985 , H01L2023/4043 , H01L2023/4087 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/10253 , H01L2924/15311 , H01L2924/19105 , H01L2924/00
摘要： Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.
摘要翻译： 提供半导体封装结构，其被设计成具有与第一级芯片模块整体封装的液体冷却器。 特别地，用于将第一级芯片封装结构中的液体冷却器装置整体封装的装置包括其中液体冷却器装置直接热耦合到安装在柔性芯片载体衬底上的集成电路芯片倒装芯片的背面的结构。 液体冷却器装置通过金属加强结构机械耦合到封装基板，金属加强结构结合到柔性封装基板上，以向柔性封装基板提供机械刚性。
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