公开(公告)号：US6080658A

公开(公告)日：2000-06-27

申请号：US151061

申请日：1998-09-10

Applicant: Lu-Shiang Huang ,  Kuan-Yu Fu

Inventor： Lu-Shiang Huang ,  Kuan-Yu Fu

IPC: H01L21/311 ,  H01L21/4763 ,  H01L21/302

CPC classification number: H01L21/31116

Abstract: A device manufacturing method prevents damage from plasma charging and vertical cross talk. The method comprises the steps of forming an insulating layer over a substrate that has a MOS device and source/drain regions already formed thereon. The insulating layer is formed by a non-plasma operation so that plasma damage is avoided. Thereafter, a conductive layer is formed over the substrate. The conductive layer is used to channel away excess charges produced during subsequent plasma operations, thereby balancing electric potential and preventing damage to the device from current flow. Subsequently, an inter-layer dielectric layer is formed over the conductive layer, and then the inter-layer dielectric layer, the conductive layer and the insulating layer are patterned to form an opening that exposes the source/drain region. Finally, a conventional method is used to form another insulating layer over the exposed conductive layer in order to prevent direct contact with subsequently formed metallic contacts inside the opening.

Abstract translation: 装置制造方法可防止等离子体充电和垂直串扰的损坏。 该方法包括以下步骤：在已经形成有MOS器件和源极/漏极区的衬底上形成绝缘层。 通过非等离子体操作形成绝缘层，从而避免等离子体损伤。 此后，在衬底上形成导电层。 导电层用于导出在随后的等离子体操作期间产生的过量电荷，从而平衡电势并防止从电流流出对器件的损坏。 随后，在导电层之上形成层间电介质层，然后对层间电介质层，导电层和绝缘层进行图案化以形成露出源极/漏极区的开口。 最后，使用常规方法在暴露的导电层上形成另一个绝缘层，以防止与开口内的随后形成的金属触点的直接接触。

公开(公告)号：US06255696B1

公开(公告)日：2001-07-03

申请号：US09280645

申请日：1999-03-29

Applicant: Kuan-Yu Fu

Inventor： Kuan-Yu Fu

IPC: H01L2978

CPC classification number: H01L29/66492 ,  H01L29/1083 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A retrograde ESD (electrostatic discharge) protection apparatus is disclosed. In a MOSFET (metal-oxide-semiconductor field effect transistor) having a source region, a drain region, a gate region, and a LDD (Lightly-Doped Drain) region, the ESD protection regions are implanted using heavy doped method under LDD region such that the implantation profile is optimized. The optimized profile is that the concentration of ESD protection region is heaviest at the source/drain junction region.

Abstract translation: 公开了一种逆行ESD（静电放电）保护装置。 在具有源极区域，漏极区域，栅极区域和LDD（轻掺杂漏极）区域的MOSFET（金属氧化物半导体场效应晶体管）中，在LDD区域内使用重掺杂法注入ESD保护区域 使得植入轮廓被优化。 优化的特征是ESD源极/漏极结区域的ESD保护区域的浓度最大。

公开(公告)号：US6084458A

公开(公告)日：2000-07-04

申请号：US86380

申请日：1998-05-28

Applicant: Kuan-Yu Fu

Inventor： Kuan-Yu Fu

IPC: H03K17/687

CPC classification number: H03K17/6874

Abstract: A bi-directional transistor structure is provided, which can help solve the problem of degraded performance due to hot carrier injection (HCI) effect that is otherwise prominent in conventional bi-directional transistors. This bi-directional transistor structure includes the following: a first diode element whose negative end is connected to the first I/O port and whose positive end is connected to a first node; a first MOS transistor element whose first source/drain electrode is connected to the first node connected to the positive end of the first diode element, whose second source/drain electrode is connected to the second I/O port and whose gate is connected to a second node; a second diode element whose negative end is connected to the second I/O port and whose positive end is connected to a third node; and a second MOS transistor element whose first source/drain electrode is connected to the first I/O port, whose second source/drain electrode is connected to the third node connected to the positive end of the second diode element and whose gate is connected to the second node connected to the gate of the first MOS transistor element. In the foregoing bi-directional transistor structure, the first and second MOS transistor elements can be either NMOS transistors or PMOS transistors. This bi-directional transistor structure has an advantage over the prior art since two different routes are provided for the directional operations, which can help prevent the unsymmetrical HCI effect.

Abstract translation: 提供了一种双向晶体管结构，这有助于解决由于常规双向晶体管的热载流子注入（HCI）效应而导致的性能下降的问题。 该双向晶体管结构包括：第一二极管元件，其负端连接到第一I / O端口，其正端连接到第一节点; 第一MOS晶体管元件，其第一源极/漏极连接到与第一二极管元件的正极连接的第一节点，其第二源极/漏极连接到第二I / O端口，并且其栅极连接到 第二节点 第二二极管元件，其负端连接到第二I / O端口，其正端连接到第三节点; 以及第二MOS晶体管元件，其第一源极/漏极连接到第一I / O端口，其第二源极/漏极连接到连接到第二二极管元件的正极的第三节点，并且其栅极连接到 所述第二节点连接到所述第一MOS晶体管元件的栅极。 在上述双向晶体管结构中，第一和第二MOS晶体管元件可以是NMOS晶体管或PMOS晶体管。 该双向晶体管结构相对于现有技术具有优点，因为为方向性操作提供了两条不同的路线，这有助于防止不对称的HCI效应。

公开(公告)号：US6064095A

公开(公告)日：2000-05-16

申请号：US72156

申请日：1998-05-04

Applicant: Kuan-Yu Fu

Inventor： Kuan-Yu Fu

IPC: H01L27/02 ,  H01L23/62 ,  H01L29/00 ,  H01L29/76

CPC classification number: H01L27/0266

Abstract: A layout design for an electrostatic discharge protection device formed above a first type of semiconductor substrate. This electrostatic discharge protection device comprises a gate region having a tortuous but continuous structure located above the first type semiconductor substrate, a common source region in the first type semiconductor substrate located on one side of the gate region, a multiple of separate drain regions in the first type semiconductor substrate located on the other side of the gate region, a multiple of contact openings distributed over the common source region and the drain regions, and, a conductive runner having a width narrower than the drain region electrically connected to each drain region.

Abstract translation: 一种形成在第一种类型的半导体衬底之上的静电放电保护器件的布局设计。 该静电放电保护装置包括具有位于第一类型半导体衬底上方的曲折但连续结构的栅极区域，位于栅极区一侧的第一类型半导体衬底中的公共源极区域， 位于栅极区域另一侧的第一类型半导体衬底，分布在公共源极区域和漏极区域上的多个接触开口，以及导电流道，其宽度窄于与每个漏极区域电连接的漏极区域。

公开(公告)号：US06436798B2

公开(公告)日：2002-08-20

申请号：US09382146

申请日：1999-08-24

Applicant: Kuan-Yu Fu

Inventor： Kuan-Yu Fu

IPC: H01L21425

CPC classification number: H01L29/7834 ,  H01L21/28114 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/42376 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66787

Abstract: A method of fabricating a MOSFET device with a multiple T-shaped gate has the following steps. A substrate with an active region and a non-active region is provided, wherein the active region has a plurality of trenches, and the non-active region has a plurality shallow trench isolation structures. A thin insulating layer and a conducting layer are formed in the trenches. The conducting layer is defined to form a gate. The device is implanted with first ions. Then, the device is further implanted with second ions by using a mask, wherein the mask expose the trenches of the active region, and the opening of the mask is wider than the trench. The MOSFET device has at least the following structures. There is a substrate with an active region and a non-active region, wherein the active region has a plurality of trenches and the non-active region has a plurality of shallow trench isolation structures. There is a multiple T-shaped gate with a first part and a second part, wherein the first part is formed between two trenches on the substrate and the second part is formed in the trenches of the active region. There is a source/drain region with a shallow doped region and a deep doped region. The multiple T-shaped gate increases the channel width of the MOSFET device and decreases the short channel effect of the high integrity ICs.

Abstract translation: 制造具有多个T形栅极的MOSFET器件的方法具有以下步骤。 提供了具有有源区和非有源区的衬底，其中有源区具有多个沟槽，并且非有源区具有多个浅沟槽隔离结构。 在沟槽中形成薄的绝缘层和导电层。 导电层被定义为形成栅极。 器件植入第一个离子。 然后，通过使用掩模将器件进一步注入第二离子，其中掩模暴露有源区的沟槽，并且掩模的开口比沟槽更宽。 MOSFET器件至少具有以下结构。 存在具有有源区和非有源区的衬底，其中有源区具有多个沟槽，而非有源区具有多个浅沟槽隔离结构。 存在具有第一部分和第二部分的多个T形门，其中第一部分形成在衬底上的两个沟槽之间，并且第二部分形成在有源区域的沟槽中。 存在具有浅掺杂区域和深掺杂区域的源极/漏极区域。 多个T形栅极增加了MOSFET器件的沟道宽度，并降低了高完整性IC的短沟道效应。

公开(公告)号：US6052311A

公开(公告)日：2000-04-18

申请号：US114004

申请日：1998-07-10

Applicant: Kuan-Yu Fu

Inventor： Kuan-Yu Fu

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  G11C7/00

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L29/42336 ,  H01L29/7883 ,  G11C2216/10

Abstract: An electrically erasable programmable read only flash memory having a buried floating gate structure buries the floating gate within the substrate. The source and drain regions are located beside the floating gate, and the control gate is located on the surface of the substrate and above the floating gate. In the program mode of read only flash memory based on the structure of this invention, the tunneling effect occurs between the floating gate and control gate to reduce leakage current and to raise the programming rate, which has the advantage of increasing the integration of memory cells.

Abstract translation: 具有埋置浮动栅极结构的电可擦除可编程只读闪存将衬底内的浮动栅极埋入其中。 源极和漏极区域位于浮置栅极旁边，并且控制栅极位于衬底的表面上并且位于浮动栅极之上。 在基于本发明的结构的只读闪存的编程模式中，在浮栅和控制栅之间发生隧道效应，以减少漏电流并提高编程速率，这具有增加存储单元的集成的优点 。

公开(公告)号：US5963831A

公开(公告)日：1999-10-05

申请号：US294981

申请日：1999-04-19

Applicant: Kuan-Yu Fu

Inventor： Kuan-Yu Fu

IPC: H01L23/522 ,  H01L21/44 ,  H01L21/326 ,  H01L21/82 ,  H01L23/48

CPC classification number: H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S438/927 ,  Y10S438/957

Abstract: A method of fabricating an interconnect structure having improved electromigration resistance. Two conductive lines are formed over a substrate and isolated by a dielectric layer. A contact/via array including a plurality of row contact/vias and column contact/vias are formed within the dielectric layer and electrically connect to the two conductive lines. The load resistors are respectively inserted into the two conductive lines close to the contact/via array. The load resistors are parallel to each other and disposed to its corresponding contact/via array. The load resistors having various resistances are formed by a plurality of slots with various lengths, which are filled with dielectrics. Accordingly, the current paths from one conductive line to the other conductive line through the contact/vias and the load resistors corresponding to the two conductive lines have identical equivalent resistance.

Abstract translation: 一种制造具有改善的电迁移电阻的互连结构的方法。 两个导线形成在衬底上并由电介质层隔离。 包括多个行接触/通孔和列接触/通孔的接触/通孔阵列形成在电介质层内并且电连接到两个导电线。 负载电阻分别插入靠近触点/通孔阵列的两条导线。 负载电阻彼此平行并且设置在其对应的接触/通孔阵列上。 具有各种电阻的负载电阻由具有各种长度的多个槽形成，其中填充有电介质。 因此，通过接触/通孔和对应于两个导线的负载电阻器从一条导线到另一导线的电流路径具有相同的等效电阻。

公开(公告)号：US07307311B2

公开(公告)日：2007-12-11

申请号：US10072362

申请日：2002-02-07

Applicant: Kuan-Yu Fu

Inventor： Kuan-Yu Fu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/7834 ,  H01L21/28114 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/42376 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66787

Abstract: A method of fabricating a MOSFET device with a multiple T-shaped gate has the following steps. A substrate with an active region and a non-active region is provided, wherein the active region has a plurality of trenches, and the non-active region has a plurality shallow trench isolation structures. A thin insulating layer and a conducting layer are formed in the trenches. The conducting layer is defined to form a gate. The device is implanted with first ions. Then, the device is further implanted with second ions by using a mask, wherein the mask expose the trenches of the active region, and the opening of the mask is wider than the trench. The MOSFET device has at least the following structures. There is a substrate with an active region and a non-active region, wherein the active region has a plurality of trenches and the non-active region has a plurality of shallow trench isolation structures. There is a multiple T-shaped gate with a first part and a second part, wherein the first part is formed between two trenches on the substrate and the second part is formed in the trenches of the active region. There is a source/drain region with a shallow doped region and a deep doped region. The multiple T-shaped gate increases the channel width of the MOSFET device and decreases the short channel effect of the high integrity ICs.

Abstract translation: 制造具有多个T形栅极的MOSFET器件的方法具有以下步骤。 提供了具有有源区和非有源区的衬底，其中有源区具有多个沟槽，并且非有源区具有多个浅沟槽隔离结构。 在沟槽中形成薄的绝缘层和导电层。 导电层被定义为形成栅极。 器件植入第一个离子。 然后，通过使用掩模将器件进一步注入第二离子，其中掩模暴露有源区的沟槽，并且掩模的开口比沟槽更宽。 MOSFET器件至少具有以下结构。 存在具有有源区和非有源区的衬底，其中有源区具有多个沟槽，而非有源区具有多个浅沟槽隔离结构。 存在具有第一部分和第二部分的多个T形门，其中第一部分形成在衬底上的两个沟槽之间，并且第二部分形成在有源区域的沟槽中。 存在具有浅掺杂区域和深掺杂区域的源极/漏极区域。 多个T形栅极增加了MOSFET器件的沟道宽度，并降低了高完整性IC的短沟道效应。

公开(公告)号：US06268269B1

公开(公告)日：2001-07-31

申请号：US09474846

申请日：1999-12-30

Applicant: Ming-Tsan Lee ,  Chuan H. Liu ,  Kuan-Yu Fu

Inventor： Ming-Tsan Lee ,  Chuan H. Liu ,  Kuan-Yu Fu

IPC: H01L21322

CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28211

Abstract: A fabrication method for an oxide layer with reduced interface-trapped charges, which is applicable to the fabrication of a gate oxide layer of a flash memory device, is described. The method includes conducting a first inert ambient annealing process, followed by growing an oxide layer on the silicon substrate. A second inert ambient annealing process is then conducted on the oxide layer. Carbon ions are then incorporated into the interface between the oxide layer and the silicon substrate, followed by a third ambient annealing process.

Abstract translation: 描述了可应用于制造闪速存储器件的栅极氧化物层的具有减少的界面俘获电荷的氧化物层的制造方法。 该方法包括进行第一惰性环境退火工艺，随后在硅衬底上生长氧化物层。 然后在氧化物层上进行第二惰性环境退火工艺。 然后将碳离子并入到氧化物层和硅衬底之间的界面中，随后进行第三环境退火处理。

公开(公告)号：US06249139B1

公开(公告)日：2001-06-19

申请号：US09393054

申请日：1999-09-09

Applicant: Kuan-Yu Fu ,  Mainn-Gwo Chen ,  Chuan H. Liu

Inventor： Kuan-Yu Fu ,  Mainn-Gwo Chen ,  Chuan H. Liu

IPC: G01R3126

CPC classification number: G01R31/129 ,  G01R31/2648

Abstract: A method is described for taking a lifetime measurement of an ultra-thin dielectric layer. In order to discover the life time of the ultra-thin dielectric layer, the measurement comprises using about one half of a stress voltage to measure a time-dependent leakage current of the ultra-thin dielectric layer.

Abstract translation: 描述了一种对超薄介电层进行寿命测量的方法。 为了发现超薄电介质层的寿命，测量包括使用大约一半的应力电压来测量超薄电介质层的时间依赖性漏电流。