公开(公告)号：US5631588A

公开(公告)日：1997-05-20

申请号：US236227

申请日：1994-04-29

Applicant: Luca Bertolini

Inventor： Luca Bertolini

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/78 ,  H02H9/04 ,  H03K17/00 ,  H03K17/08 ,  H03K17/082 ,  H03K17/615 ,  H03K17/687 ,  H05B41/14

CPC classification number: H02H9/047 ,  H03K17/0822 ,  H03K2217/0036

Abstract: A power stage of quasi-complementary symmetry, including a common-source FET and a common-drain FET, with a reduced absorption of current under the conditions of high impedance of the output. The driving node of the upper (common-drain) transistor from is decoupled from the output node of the stage, preventing the current generator Id, which discharges the control node, from absorbing current from the load connected to the output stage, during a phase of high output impedance. This is preferably realized by using a field effect transistor which has its gate connected to the output node of the stage, and is connected to provide the current drawn from the discharge generator of the driving node of the upper common-drain transistor, absorbing it from the supply node VDD instead of absorbing it from the voltage overdriven node Vb. This alternative solution avoids excessive loading of the high-voltage supply, and is particularly useful when the overdriven node Vb drives multiple output stages.

Abstract translation: 包括共源FET和共漏极FET在内的准互补对称功率级，在输出的高阻抗条件下电流吸收减小。 上级（公共漏极）晶体管的驱动节点与级的输出节点分离，从而防止在控制节点放电的电流发生器Id在相位期间从连接到输出级的负载吸收电流 的高输出阻抗。 这优选地通过使用其栅极连接到级的输出节点的场效应晶体管来实现，并且被连接以提供从上部公共漏极晶体管的驱动节点的放电发生器提取的电流， 供电节点VDD而不是从电压过驱动节点Vb吸收电源节点。 该替代解决方案避免了高压电源的过度负载，并且在过驱动节点Vb驱动多个输出级时特别有用。

公开(公告)号：US6057663A

公开(公告)日：2000-05-02

申请号：US131249

申请日：1998-08-05

Applicant: Ezio Galbiati ,  Michele Boscolo ,  Luca Bertolini

Inventor： Ezio Galbiati ,  Michele Boscolo ,  Luca Bertolini

IPC: H02P6/08 ,  H02P6/28 ,  G05B11/28

CPC classification number: H02P6/085 ,  H02P6/28

Abstract: The control of the current in a PWM mode through independently controlled windings of a multi-phase motor driven in a "bipolar" mode is implemented by employing only two sense resistors and related control loops. This is so regardless of the actual number of windings of the motor.

Abstract translation: 通过独立控制的以“双极”模式驱动的多相电动机的绕组来控制PWM模式中的电流通过仅使用两个检测电阻器和相关的控制回路来实现。 无论电机的实际绕组数如何，都是如此。

公开(公告)号：US5453678A

公开(公告)日：1995-09-26

申请号：US83721

申请日：1993-06-24

Applicant: Luca Bertolini ,  Roberto Gariboldi

Inventor： Luca Bertolini ,  Roberto Gariboldi

IPC: G05F1/56 ,  G05F1/46 ,  G06K7/00 ,  H02H1/04

CPC classification number: H02H1/043 ,  G05F1/468 ,  G06K7/0008

Abstract: A regulator including a power element between the input terminal and output terminal; and a regulating loop including a differential stage for comparing the output voltage of the regulator with a reference voltage and accordingly driving a gain stage connected to the power element. The output voltage is picked up by the differential stage via a resistive divider, the resistance of which varies according to the value of a logic signal at a control input. When the resistance of the divider changes, the inputs of the differential stage are so unbalanced as to produce an output voltage up or down ramp equal to the slew rate of the regulating loop and proportional to the bias current of the differential stage. Over the up ramp, the shorting protection circuit is turned off for a predetermined time .tau., whereas, over the down ramp, a stage is turned on for absorbing the discharge current of the capacitive load.

Abstract translation: 一种调节器，包括输入端子和输出端子之间的功率元件; 以及调节回路，其包括用于将调节器的输出电压与参考电压进行比较的差分级，并因此驱动连接到功率元件的增益级。 输出电压由差分级通过电阻分压器拾取，电阻分压器根据控制输入端的逻辑信号值而变化。 当分压器的电阻变化时，差分级的输入是不平衡的，以产生输出电压上升或下降斜坡等于调节回路的转换速率并与差动级的偏置电流成正比。 在上升斜坡上，短路保护电路关闭预定时间τ，而在下降斜坡上，一个阶段被接通以吸收容性负载的放电电流。

公开(公告)号：US20080246345A1

公开(公告)日：2008-10-09

申请号：US11573078

申请日：2005-08-03

Applicant: Michel Zecri ,  Luca Bertolini ,  Patrice Besse ,  Maryse Bafleur ,  Nicolas Nolhier

Inventor： Michel Zecri ,  Luca Bertolini ,  Patrice Besse ,  Maryse Bafleur ,  Nicolas Nolhier

IPC: H03K17/082

CPC classification number: H03K17/0822

Abstract: A semiconductor switch arrangement (300) comprises a bipolar transistor (302) and a semiconductor power switch (301) having an input node (306), an output node (304) and a control node (305) for allowing a current path to be formed between the input node (306) and the output node (307). The bipolar transistor (302) is coupled between the input node (306) and the control node (305) such that upon receiving an electro-static discharge pulse the bipolar transistor (302) allows a current to flow from the input node (306) to the control node (305) upon a pre-determined voltage being exceeded at the input node (306) to allow the control node (305) to cause a current to flow from the input node (306) to the output node (307). Thus, the bipolar transistor device protects the semiconductor switch device, such as an LDMOS device, against ESD, namely protection against power surges of, say, several amperes in less than 1 usec.

Abstract translation: 半导体开关装置（300）包括双极晶体管（302）和具有输入节点（306）的半导体功率开关（301），输出节点（304）和控制节点（305），用于允许电流路径为 形成在输入节点（306）和输出节点（307）之间。 双极晶体管（302）耦合在输入节点（306）和控制节点（305）之间，使得当接收到静电放电脉冲时，双极晶体管（302）允许电流从输入节点（306）流出， 在所述输入节点（306）超过预定电压以允许所述控制节点（305）使电流从所述输入节点（306）流向所述输出节点（307）的情况下，发送到所述控制节点（305） 。 因此，双极晶体管器件保护诸如LDMOS器件的半导体开关器件免受ESD，即在小于1 usec内防止诸如几安培的功率浪涌。

公开(公告)号：US6111429A

公开(公告)日：2000-08-29

申请号：US79131

申请日：1998-05-14

Applicant: Luca Bertolini

Inventor： Luca Bertolini

IPC: H03K3/356 ,  H03K17/10 ,  H03K19/0175

CPC classification number: H03K3/356113 ,  H03K17/102

Abstract: A circuit for shifting the voltage level of a digital signal, comprising a first pair of transistors of a first polarity, which are connected to a high-voltage line, and a second pair of transistors of a second polarity, which are connected to a ground line; the first and second pairs of transistors are connected to each other by means of the drain terminals of the respective transistors; an input voltage is applied to the gate terminals of the first pair of transistors. The circuit further includes a secondary circuit for leveling the gate voltages of the transistors of the first and second pairs, which is connected between the first and second pairs of transistors and whereto at least one reference voltage is applied. The circuit also includes an output stage, whose output is a voltage which is shifted in level with respect to the input voltage. The secondary circuit limits the gate-source voltage value of the first pair of transistors to a value which is independent of the voltage value of the high-voltage line, so as to prevent damage to the first pair of transistors.

Abstract translation: 一种用于移动数字信号的电压电平的电路，包括连接到高电压线的第一极性的第一对晶体管和第二极性的第二对晶体管连接到地 线; 第一和第二对晶体管通过相应晶体管的漏极端子彼此连接; 输入电压被施加到第一对晶体管的栅极端子。 该电路还包括用于对连接在第一和第二对晶体管之间的第一和第二对晶体管的栅极电压进行调平的次级电路，并且至少施加至少一个参考电压。 电路还包括输出级，其输出是相对于输入电压在电平上移位的电压。 次级电路将第一对晶体管的栅极 - 源极电压值限制为与高压线的电压值无关的值，以防止损坏第一对晶体管。

公开(公告)号：US11760456B2

公开(公告)日：2023-09-19

申请号：US17176731

申请日：2021-02-16

Applicant: Nicola Varini ,  Otto Varini ,  Luca Bertolini

Inventor： Nicola Varini ,  Otto Varini ,  Luca Bertolini

IPC: B63H9/065 ,  B63H9/08

CPC classification number: B63H9/065 ,  B63H9/08 ,  B63H2009/086

Abstract: A sail for the propulsion of elements of transport, which comprises a sheet-like body made of flexible material which is connected, along one of its edges, to a supporting mast, connected to an element of transport. At least one stiffening rib is associated with the sheet-like body and is accommodated in a respective pocket which is formed in the sheet-like body and extends for at least one portion of the sheet-like body comprised between the supporting mast and the edge of the sheet-like body that is opposite to the one connected to the supporting mast; the rib has, or can assume on command, a substantially arc-like shape adapted to generate lift. Elements are further provided for varying the orientation of a concave part of the rib with respect to the supporting mast.

公开(公告)号：US07916439B2

公开(公告)日：2011-03-29

申请号：US11573078

申请日：2005-08-03

Applicant: Michel Zecri ,  Luca Bertolini ,  Patrice Besse ,  Maryse Bafleur ,  Nicolas Nolhier

Inventor： Michel Zecri ,  Luca Bertolini ,  Patrice Besse ,  Maryse Bafleur ,  Nicolas Nolhier

IPC: H02H3/22

CPC classification number: H03K17/0822

Abstract: A semiconductor switch arrangement comprises a bipolar transistor and a semiconductor power switch having an input node, an output node and a control node for allowing a current path to be formed between the input node and the output node. The bipolar transistor is coupled between the input node and the control node such that upon receiving an electro-static discharge pulse the bipolar transistor allows a current to flow from the input node to the control node upon a predetermined voltage being exceeded at the input node to allow the control node to cause a current to flow from the input node to the output node. Thus, the bipolar transistor device protects the semiconductor switch device, such as an LDMOS device, against ESD, namely protection against power surges of, say, several amperes in less than 1 usec.

Abstract translation: 半导体开关装置包括双极晶体管和具有输入节点，输出节点和控制节点的半导体功率开关，用于允许在输入节点和输出节点之间形成电流路径。 双极晶体管耦合在输入节点和控制节点之间，使得当接收到静电放电脉冲时，双极晶体管允许电流在输入节点超过预定电压时从输入节点流向控制节点 允许控制节点引起电流从输入节点流向输出节点。 因此，双极晶体管器件保护诸如LDMOS器件的半导体开关器件免受ESD，即在小于1 usec内防止诸如几安培的功率浪涌。

公开(公告)号：US06271567B1

公开(公告)日：2001-08-07

申请号：US09227946

申请日：1999-01-11

Applicant: Massimo Pozzoni ,  Paolo Cordini ,  Domenico Rossi ,  Giorgio Pedrazzini ,  Paola Galbiati ,  Michele Palmieri ,  Luca Bertolini

Inventor： Massimo Pozzoni ,  Paolo Cordini ,  Domenico Rossi ,  Giorgio Pedrazzini ,  Paola Galbiati ,  Michele Palmieri ,  Luca Bertolini

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed. The special interposition separates and shields the sensitive circuits from the power device whose oversupply or belowground effect is not countered by specific circuit arrangements.

Abstract translation: 在包括功率DMOS晶体管的结隔离集成电路中，形成在相应的阱区域中或者在相反导电类型的衬底上的隔离的外延区域中形成的电路形成在对供过剩和/或地下效应敏感的不同隔离区域中。 这些影响是由耦合到电源轨或地的各个功率DMOS晶体管引起的。 这些效果可以通过特定形状的布置布置来替代地控制，并且可以被有效地保护免受两种影响。 这通过介于敏感电路的区域和包含不形成替代可实施的电路布置的功率DMOS晶体管的区域来实现，该区域包含耦合到电源轨的功率DMOS晶体管或接地导轨， 可替代地实施的布置形成。 特殊插件将灵敏电路与供电或地下效应不受特定电路布置的电源设备分离和屏蔽。

公开(公告)号：US6072339A

公开(公告)日：2000-06-06

申请号：US185917

申请日：1998-11-04

Applicant: Luca Bertolini

Inventor： Luca Bertolini

IPC: G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC classification number: G01R19/0023

Abstract: A current sensing circuit with high input impedance comprises a first transconductance amplifier connected across the terminals of a resistor, through which a current to be measured flows. A voltage amplifier is cascade-connected to the first transconductance amplifier. A second transconductance amplifier is feedback connected between an output of the voltage amplifier and a virtual ground node of the voltage amplifier. A ratio between the output voltage of the voltage amplifier and the voltage across the resistor are equal, in absolute value, to a ratio of the transconductances of the first and second transconductance amplifiers.

Abstract translation: 具有高输入阻抗的电流感测电路包括跨越电阻器的端子连接的第一跨导放大器，待测电流流过该电阻。 电压放大器级联连接到第一跨导放大器。 第二跨导放大器反馈连接在电压放大器的输出端和电压放大器的虚拟接地节点之间。 电压放大器的输出电压与电阻两端的电压之间的比值绝对值等于第一和第二跨导放大器的跨导比。