公开(公告)号：US06438669B2

公开(公告)日：2002-08-20

申请号：US08813687

申请日：1997-03-07

申请人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

发明人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

IPC分类号： G06F1300

CPC分类号： G11C7/1006

摘要： A non-volatile memory device that comprises an internal bus for the transmission of data and other information of the memory to output pads; a timer; and an enabling/disabling circuit for enabling and disabling access to the internal bus; the timer controlling the internal bus to transmit information signals of the memory device that originate from local auxiliary lines over the internal bus when the bus is in an inactive period during a normal memory data reading cycle; the timer controlling the enabling/disabling means to allow/deny access to the internal bus on the part of the information signals or of the data from or to the memory.

摘要翻译： 一种非易失性存储器件，包括用于将数据和存储器的其它信息传输到输出焊盘的内部总线; 一个计时器 以及用于启用和禁用访问内部总线的启用/禁用电路; 所述定时器控制所述内部总线，以在所述总线在正常存储器数据读取周期期间处于非活动时段期间，通过所述内部总线发送来自所述本地辅助线路的存储器件的信息信号; 所述定时器控制所述启用/禁用装置允许/拒绝部分所述信息信号或来自所述存储器的数据的所述内部总线的访问。

公开(公告)号：US5815437A

公开(公告)日：1998-09-29

申请号：US813171

申请日：1997-03-07

申请人： Luigi Pascucci ,  Antonio Barcella ,  Paolo Rolandi ,  Marco Fontana

发明人： Luigi Pascucci ,  Antonio Barcella ,  Paolo Rolandi ,  Marco Fontana

IPC分类号： G11C17/00 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C29/00 ,  G11C11/34 ,  G11C7/00

CPC分类号： G11C29/70 ,  G11C7/10

摘要： A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells. The managing device comprises: at least one bidirectional internal bus for the transfer of data from and to the memory; a redundancy management line that is associated with the internal bus; means for enabling/disabling the transmission, over the internal bus, of the data from the memory toward the outside; means for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means for enabling/disabling the connection between the outside of the memory and the redundancy line during the reading of the memory matrix and during its programming.

摘要翻译： 一种数据输入/输出管理装置，特别是包括至少一个存储器单元矩阵的非易失性存储器。 管理设备包括：至少一个双向内部总线，用于将数据从存储器传送到存储器; 与内部总线相关联的冗余管理线; 用于启用/禁用内部总线上的数据从存储器向外部的传输的装置; 用于启用/禁用其源不同于存储器矩阵的数据部分访问内部总线的装置，用于传输到存储器矩阵; 以及用于在读取存储器矩阵期间和在其编程期间启用/禁用存储器外部与冗余线之间的连接的装置。

公开(公告)号：US5841728A

公开(公告)日：1998-11-24

申请号：US724495

申请日：1996-09-30

申请人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

发明人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

IPC分类号： G11C8/12 ,  G11C8/14 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C8/14

摘要： The memory device in accordance with the present invention has hierarchical row decoding architecture and comprises at least one main decoder and a plurality of secondary decoders. The decoders have outputs coupled to a plurality of word lines respectively through a plurality of auxiliary lines having first ends respectively connected to said outputs and second ends respectively connected to intermediate points of the word lines.

摘要翻译： 根据本发明的存储器件具有分级行解码架构，并且包括至少一个主解码器和多个辅助解码器。 解码器具有通过分别连接到分别连接到字线的中间点的所述输出和第二端的多个辅助线耦合到多个字线的输出。

公开(公告)号：US5821788A

公开(公告)日：1998-10-13

申请号：US790832

申请日：1997-01-30

申请人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

发明人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

IPC分类号： G11C5/14 ,  H03L7/00

CPC分类号： G11C5/143

摘要： A power-on-reset (P.O.R.) circuit produces a power-on-reset (P.O.R.) signal whose an amplitude tracks the voltage on a supply node until it exceeds a certain threshold. The circuit has a first monitoring and comparing circuit portion including at least a nonvolatile memory element having a control gate coupled to the supply node, a first current terminal coupled to a ground node, and a second current terminal coupled to a first node which is capacitively coupled to the supply node. The circuit further includes a second circuit portion that includes an intrinsically unbalanced bistable circuit, having a node that intrinsically is in a high state at power-on coupled to the first node that is intrinsically in a low state at power-on coupled to the input of an output buffer.

摘要翻译： 上电复位（P.O.R.）电路产生上电复位（P.O.R.）信号，其幅度跟踪供电节点上的电压，直到其超过某个阈值。 该电路具有第一监视和比较电路部分，该电路部分至少包括具有耦合到电源节点的控制栅极的非易失性存储器元件，耦合到接地节点的第一电流端子和耦合到电容性的第一节点的第二电流端子 耦合到供应节点。 该电路还包括第二电路部分，该第二电路部分包括本质上不平衡的双稳态电路，其具有在上电时本质上处于处于高状态的节点，所述节点在与所述输入端相连的上电时本质上处于处于低电平状态 的输出缓冲区。

公开(公告)号：US5659498A

公开(公告)日：1997-08-19

申请号：US684406

申请日：1996-07-19

申请人： Luigi Pascucci ,  Paolo Rolandi ,  Antonio Barcella ,  Marco Fontana

发明人： Luigi Pascucci ,  Paolo Rolandi ,  Antonio Barcella ,  Marco Fontana

IPC分类号： G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C11/00

CPC分类号： G11C7/20 ,  H03K3/356008 ,  H03K3/356104

摘要： A latch circuit that is intentionally unbalanced, so that a first output reaches ground voltage and a second output reaches a supply voltage. The latch circuit may be used with a fully static low-consumption fuse circuit which reverses the first and second outputs of the latch circuit when the fuse is in an unprogrammed state, but does not change the outputs of the latch circuit in the programmed state. In particular, the latch circuit has a first transistor of a first polarity series connected at a first output node with a second transistor of a second polarity between a supply voltage and a ground voltage. A third transistor of the first polarity is series connected at a second output node with a fourth transistor of the second polarity between the supply voltage and the ground voltage. The gate terminals of the first and second transistors are connected to the second output, while the gate terminals of the third and fourth transistors are connected to the first output. The first and third transistors have thresholds which are mutually different, and the second and fourth transistors have thresholds which are mutually different, so that the first output reaches ground voltage and the second output reaches the supply voltage. This circuit can be combined with a fuse circuit, such as a dual gate transistor.

摘要翻译： 有意不平衡的锁存电路，使得第一输出达到地电压，第二输出达到电源电压。 当熔断器处于未编程状态时，锁存电路可以与完全静态的低功耗熔丝电路一起使用，该电路使锁存电路的第一和第二输出反向，但在编程状态下不改变锁存电路的输出。 特别地，锁存电路具有第一极性串联的第一晶体管，在第一输出节点处连接有电源电压和接地电压之间的第二极性的第二晶体管。 第一极性的第三晶体管在第二输出节点处串联连接在电源电压和接地电压之间的第二极性的第四晶体管。 第一和第二晶体管的栅极端子连接到第二输出端，而第三和第四晶体管的栅极端子连接到第一输出端。 第一和第三晶体管具有相互不同的阈值，并且第二和第四晶体管具有相互不同的阈值，使得第一输出达到接地电压，第二输出达到电源电压。 该电路可以与诸如双栅极晶体管的熔丝电路组合。

公开(公告)号：US5754483A

公开(公告)日：1998-05-19

申请号：US835033

申请日：1997-03-27

申请人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

发明人： Luigi Pascucci ,  Paolo Rolandi ,  Marco Fontana ,  Antonio Barcella

IPC分类号： G11C16/06 ,  G11C7/14 ,  G11C16/28 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C16/28

摘要： A reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders, where the memory is divided into at least two memory half-matrices that are arranged on different half-planes. The circuit includes, for each one of the at least two memory half-matrices, a reference unit for each one of the at least two memory half-matrices and an associated unit for reproducing the propagation of the signals along the reference unit. The reference unit and the associated propagation reproduction unit have a structure that is identical to each generic word line of the memory device. The reference and propagation reproduction units of one of the at least two memory half-matrices are activatable upon selection of a memory cell in the other one of the at least two memory half-matrices, in order to provide a reference that is synchronous and symmetrical with respect to the selection of the memory cell for reading it and so as to preset, according to the propagation reproduction unit conditions for starting correct and certain reading of the selected memory cell.

摘要翻译： 一种参考字线和数据传播再现电路，特别是用于提供有分层解码器的非易失性存储器，其中存储器被分成至少两个布置在不同半平面上的存储器半矩阵。 对于至少两个存储器半矩阵中的每一个，电路包括用于至少两个存储器半矩阵中的每一个的参考单元和用于再现信号沿着参考单元的传播的相关单元。 参考单元和相关联的传播再现单元具有与存储器件的每个通用字线相同的结构。 所述至少两个存储器半矩阵之一的参考和传播再现单元可以在选择所述至少两个存储器半矩阵中的另一个存储器半矩阵中的存储器单元时激活，以便提供同步和对称的参考 关于选择用于读取的存储单元，并且根据用于开始选择的存储单元的正确和特定读取的传播再现单元条件来预设存储单元。

公开(公告)号：US6009041A

公开(公告)日：1999-12-28

申请号：US32272

申请日：1998-02-26

申请人： Paolo Rolandi ,  Antonio Barcella ,  Marco Fontana ,  Massimo Montanaro

发明人： Paolo Rolandi ,  Antonio Barcella ,  Marco Fontana ,  Massimo Montanaro

IPC分类号： G11C8/18 ,  G11C8/00

CPC分类号： G11C8/18

摘要： A method and circuit to trim the internal timing conditions for a semiconductor memory device including a memory matrix and circuit portions for allowing reading of the data stored in the memory matrix wherein such circuit portions include an ATD generator detecting each transition of a plurality of address terminals of the memory device to produce an ATD synchronization signal, a sense amplifier which receives an equalization a signal EQU from a generator activated by the ATD signal, and output buffers enabled by an OUTLATCH signal produced by a generator receiving the ATD signal and the EQU signal. The length of the signals is automatically trimmed according to a corresponding length code contained in a portion of the memory device.

摘要翻译： 一种用于修整包括存储矩阵和电路部分的半导体存储器件的内部定时条件的方法和电路，用于允许读取存储在矩阵中的数据，其中这些电路部分包括检测多个地址端子的每个转换的ATD发生器 产生ATD同步信号的读出放大器，从由ATD信号激活的发生器接收信号EQU的均衡的读出放大器以及由接收ATD信号的发生器和EQU信号产生的OUTLATCH信号使能的输出缓冲器 。 信号的长度根据包含在存储器件的一部分中的对应的长度码自动修整。

公开(公告)号：US6075718A

公开(公告)日：2000-06-13

申请号：US39588

申请日：1998-03-16

申请人： Marco Fontana ,  Antonio Barcella ,  Massimo Montanaro ,  Carmelo Paolino

发明人： Marco Fontana ,  Antonio Barcella ,  Massimo Montanaro ,  Carmelo Paolino

IPC分类号： G11C16/26 ,  G11C17/00

CPC分类号： G11C16/26

摘要： The method comprises the steps of detecting the trailing edge of an initialization signal, and generating a read bias signal and a read activation signal for the cell, when the trailing edge of the initialization signal is detected. The signals of read bias and read activation have a ramp-like leading edge and both signals are disabled when reading of the cell is completed. Thereby, phenomena of soft-writing of the cell are avoided, and risks of erroneous readings are reduced.

摘要翻译： 该方法包括以下步骤：当检测到初始化信号的后沿时，检测初始化信号的后沿，以及产生用于该单元的读取偏置信号和读取激活信号。 读取偏置和读取激活的信号具有斜坡状的前沿，当读取单元格完成时，两个信号都被禁止。 从而避免了对单元进行软写入的现象，并且降低了错误读数的风险。

公开(公告)号：US5959902A

公开(公告)日：1999-09-28

申请号：US30604

申请日：1998-02-25

申请人： Marco Fontana ,  Antonio Barcella

发明人： Marco Fontana ,  Antonio Barcella

IPC分类号： G11C8/08 ,  G11C16/12 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C8/08

摘要： In a first operation mode the level shifter transmits as output a logic input signal and in a second operation mode it shifts the high logic level of the input signal from a low to a high voltage. The level shifter comprises a CMOS switch and a pull-up transistor; the CMOS switch comprises an NMOS transistor and a PMOS transistor which are connected in parallel between the input and the output of the shifter and have respective control terminals connected to a first supply line at low voltage and, respectively, to a control line connected to ground in the first operation mode and to the high voltage in the second operation mode; the pull-up transistor is connected between the output of the shifter and a second supply line switchable between the low voltage and the high voltage and has a control terminal connected to the first supply line.

摘要翻译： 在第一操作模式中，电平转换器作为输出发送逻辑输入信号，并且在第二操作模式中，它将输入信号的高逻辑电平从低电平转移到高电压。 电平移位器包括CMOS开关和上拉晶体管; CMOS开关包括NMOS晶体管和PMOS晶体管，其并联连接在移位器的输入和输出之间，并且各自的控制端子以低电压连接到第一电源线，并且分别连接到连接到地的控制线 在第一操作模式和第二操作模式中的高电压; 上拉晶体管连接在移位器的输出端和可在低电压和高电压之间切换的第二电源线，并且具有连接到第一电源线的控制端子。

公开(公告)号：US06477625B1

公开(公告)日：2002-11-05

申请号：US09474932

申请日：1999-12-29

申请人： Luigi Pascucci ,  Marco Fontana

发明人： Luigi Pascucci ,  Marco Fontana

IPC分类号： G06F1206

CPC分类号： G11C7/1018

摘要： A method for reading a memory by applying control signals. The control signals include a memory enable signal, a visibility signal, and a read signal. By applying the control signals to the memory, the memory is selectively configured into any of a plurality of cycles associated with reading the memory. The different cycles include: random read, pipeline-type random read, sequential read and suspend and wait cycles. Depending upon the cycle configuration of the memory, data is selectively emitted from the memory that coincides with the externally generated address.

摘要翻译： 一种通过应用控制信号读取存储器的方法。 控制信号包括存储器使能信号，可见度信号和读取信号。 通过将控制信号施加到存储器，存储器被选择性地配置成与读取存储器相关联的多个周期中的任一个。 不同的周期包括：随机读取，流水线型随机读取，顺序读取和挂起和等待周期。 根据存储器的周期配置，选择性地从存储器发射数据，这与外部产生的地址一致。